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spi/i 2 c compatible, temperature sensor, 4-channel adc and quad voltage output dac adt7518 rev . a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features four 8-bit dacs buffered voltage output guaranteed monotonic by design over all codes 10-bit temperature-to-digital converter 10-bit 4-channel adc dc input bandwidth input range: 0 v to 2.25 v temperature range: C40c to +120c temperature sensor accu racy of typ: 0.5c supply range: 2.7 v to 5.5 v dac output range: 0 v to 2 v ref power-down current: 1 a internal 2.25 v ref option double-buffered input logic buffered reference input power-on reset to 0 v dac output simultaneous update of outputs ( ldac function) on-chip rail-to-rail output buffer amplifier spi ? , i 2 c ? , qspi?, microwire?, and dsp-compatible 4-wire serial interface smbus packet error checking (pec)-compatible 16-lead qsop package applications portable battery-powered instruments personal computers smart battery chargers telecommunications systems electronic text equipment domestic appliances process control pin configuration adt7518 top view (not to scale) v out -b 1 v out -c 16 v out -a 2 v out -d 15 v ref -in 3 ain4 14 cs 4 scl/sclk 13 gnd 5 sda/din 12 v dd 6 dout/add 11 d+/ain1 7 int/int 10 d?/ain2 8 ldac/ain3 9 04879-001 figure 1. general description the adt7518 combines a 10-bit temperature-to-digital converter, a 10-bit 4-channel adc, and a quad 8-bit dac, in a 16-lead qsop package. the part also includes a band gap temperature sensor and a 10-bit adc to monitor and digitize the temperature reading to a resolution of 0.25c. the adt7518 operates from a single 2.7 v to 5.5 v supply. the input voltage range on the adc channels is 0 v to 2.25 v, and the input bandwidth is dc. the reference for the adc channels is derived internally. the output voltage of the dac ranges from 0 v to v dd , with an output voltage settling time of 7 ms typical. the adt7518 provides two serial interface options: a 4-wire serial interface that is compatible with spi, qspi, microwire, and dsp interface standards, and a 2-wire smbus/i 2 c interface. it features a standby mode that is controlled through the serial interface. the reference for the four dacs is derived either internally or from a reference pin. the outputs of all dacs may be updated simultaneously using the software ldac function or the exter- nal ldac pin. the adt7518 incorporates a power-on reset circuit, which ensures that the dac output powers up to 0 v and remains there until a valid write takes place. the adt7518s wide supply voltage range, low supply current, and spi-/i 2 c-compatible interface make it ideal for a variety of applications, including personal computers, office equipment, and domestic appliances. it is recommended th at new designs use the adt7519 rather than the adt7518. the adt7518s internal and external temp- erature accuracy spec is only valid when not using the internal reference for the on-chip dac. the adt7519 does not have this limitation.
adt7518 rev. a | page 2 of 40 table of contents specifications ..................................................................................... 3 dac ac characteristics .............................................................. 6 functional block diagram .............................................................. 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and functional descriptions .......................... 9 te r m i no l o g y .................................................................................... 10 typical performance characteristics ........................................... 12 theory of operation ...................................................................... 17 power-up calibration ................................................................ 17 conversion speed ....................................................................... 17 function descriptionvoltage output .................................. 18 functional descriptionanalog inputs ................................. 20 adc transfer function ............................................................. 21 functional descriptionmeasurement .................................. 22 adt7518 registers .................................................................... 25 serial interface ............................................................................ 33 smbus alert response ............................................................... 38 outline dimensions ....................................................................... 40 ordering guide .......................................................................... 40 revision history 8/04data sheet changed from rev. 0 to rev. a updated format...................................................................... universal separate adt7518 from adt7516/adt7517/adt7518 data sheet........................ universal change to equation.............................................................................25 7/03revision 0: initial version
adt7518 rev. a | page 3 of 40 specifications table 1. temperature range is as fo llows: a version: C40c to +120c. v dd = 2.7 v to 5.5 v, gnd = 0 v, ref in = 2.25 v, unless otherwise noted. parameter 1 min typ max unit conditions/comments dac dc performance 2 , 3 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic over all codes. offset error 0.4 2 % of fsr gain error 0.3 2 % of fsr lower deadband 20 65 mv lower deadband exists on ly if offset error is negative. see figure 8. upper deadband 60 100 mv upper deadband exists if v ref = v dd and offset plus gain error is positive. see figure 9. offset error drift 4 C12 ppm of fsr/c gain error drift 4 C5 ppm of fsr/c dc power supply rejection ratio 4 C60 db ?v dd = 10%. dc crosstalk 4 200 v see figure 5. adc dc accuracy max v dd = 5 v. resolution 10 bits total unadjusted error (tue) 2 3 % of fsr offset error 0.5 % of fsr gain error 2 % of fsr adc bandwidth dc hz analog inputs 5 input voltage range 0 2.25 v ain1 to ain4. c4 = 0 in control configuration 3. 0 v dd v ain1 to ain4. c4 = 0 in control configuration 3. dc leakage current 1 a input capacitance 5 20 pf input resistance 10 m? thermal characteristics 6 internal temperature sensor internal reference used. averaging on. accuracy @ v dd = 3.3 v 10% 1.5 c t a = 85c. 0.5 3 c t a = 0c to +85c. 2 5 c t a = C40c to +120c. accuracy @ v dd = 5 v 5% 2 3 c t a = 0c to +85c. 3 5 c t a = C40c to +120c. resolution 10 bits equivalent to 0.25c. long-term drift 0.25 c drift over 10 years if part is operated at 55c. thermal characteristics 6 external temperature sensor external transistor = 2n3906. accuracy @ v dd = 3.3 v 10% 1.5 c t a = 85c. 3 c t a = 0c to +85c. 5 c t a = C40c to +120c. accuracy @ v dd = 5 v 5% 2 3 c t a = 0c to +85c. 3 5 c t a = C40c to +120c. resolution 10 bits equivalent to 0.25c. output source current 180 a high level. 11 a low level. thermal characteristics 6 thermal voltage output 8-bit dac output resolution 1 c
adt7518 rev. a | page 4 of 40 parameter 1 min typ max unit conditions/comments scale factor 8.97 mv/c 0 v to v ref output. t a = C40c to +120c. 17.58 mv/c 0 v to 2 v ref output. t a = C40c to +120c. conversion times single channel mode. slow adc v dd /ain 11.4 ms averaging (16 samples) on. 712 s averaging off. internal temperature 11.4 ms averaging (16 samples) on. 712 s averaging off. external temperature 24.22 ms averaging (16 samples) on. 1.51 ms averaging off. fast adc v dd /ain 712 s averaging (16 samples) on. 44.5 s averaging off. internal temperature 2.14 ms averaging (16 samples) on. 134 s averaging off. external temperature 14.25 ms averaging (16 samples) on. 890 s averaging off. round robin update rate 5 time to complete one measurement cycle through all channels. slow adc @ 25c averaging on 79.8 ms ain1 and ain2 are selected on pins 7 and 8. averaging off 4.99 ms ain1 and ain2 are selected on pins 7 and 8. averaging on 94.76 ms d+ and dC are selected on pins 7 and 8. averaging off 9.26 ms d+ and dC are selected on pins 7 and 8. fast adc @ 25c averaging on 6.41 ms ain1 and ain2 are selected on pins 7 and 8. averaging off 400.84 s ain1 and ain2 are selected on pins 7 and 8. averaging on 21.77 ms d+ and dC are selected on pins 7 and 8. averaging off 3.07 ms d+ and dC are selected on pins 7 and 8. dac external reference input 4 v ref input range 1 v dd v buffered reference. v ref input impedance >10 m? buffe red reference and power-down mode. reference feedthrough C90 db frequency = 10 khz. channel-to-channel isolation C75 db frequency = 10 khz. on-chip reference reference voltage 4 2.25 v temperature coefficient 4 80 ppm/c output characteristics 4 output voltage 7 0.001 v dd ? 0.1 v this is a measure of the minimum and maximum drive capability of the output amplifier. dc output impedance 0.5 ? short-circuit current 25 ma v dd = 5 v. 16 ma v dd = 3 v. power-up time 2.5 s coming out of power-down mode. v dd = 5 v. 5 s coming out of power-down mode. v dd = 3.3 v. digital inputs 4 input current 1 a v in = 0 v to v dd. v il , input low voltage 0.8 v v ih , input high voltage 1.89 v pin capacitance 3 10 pf all digital inputs. scl, sda glitch rejection 50 ns input filtering suppresses noise spikes of less than 50 ns. ldac pulse width 20 ns edge triggered input.
adt7518 rev. a | page 5 of 40 parameter 1 min typ max unit conditions/comments digital output digital high voltage, v oh 2.4 v i source = i sink = 200 a. output low voltage, v ol 0.4 v i ol = 3 ma. output high current, i oh 1 ma v oh = 5 v. output capacitance, c out 50 pf int/ int output saturation voltage 0.8 v i out = 4 ma. i 2 c timing characteristics 8 , 9 serial clock period, t 1 2.5 s fast mode i 2 c. see figure 2. data in setup time to scl high, t 2 50 ns data out stable after scl low, t 3 0 ns see figure 2. sda low setup time to scl low (start condition), t 4 50 ns see figure 2. sda high hold time after scl high (stop condition), t 5 50 ns see figure 2. sda and scl fall time, t 6 90 ns see figure 2. spi timing characteristics 4 , 10 cs to sclk setup time, t 1 0 ns see figure 3. sclk high pulse width, t 2 50 ns see figure 3. sclk low pulse width, t 3 50 ns see figure 3. data access time after sclk falling edge, t 4 11 35 ns data setup time prior to sclk rising edge, t 5 20 ns see figure 3. data hold time after sclk rising edge, t 6 0 ns see figure 3. cs to sclk hold time, t 7 0 s see figure 3. cs to dout high impedance, t 8 40 ns see figure 3. power requirements v dd 2.7 5.5 v v dd settling time 50 ms v dd settles to within 10% of its final voltage level. i dd (normal mode) 12 3 ma v dd = 3.3 v, v ih = v dd , and v il = gnd. 2.2 3 ma v dd = 5 v, v ih = v dd , and v il = gnd. i dd (power-down mode) 10 a v dd = 3.3 v, v ih = v dd , and v il = gnd. 10 a v dd = 5 v, v ih = v dd , and v il = gnd. power dissipation 10 mw v dd = 3.3 v. normal mode. 33 w v dd = 3.3 v. shutdown mode. 1 see the section. terminology 2 dc specifications are tested with the outputs unloaded. 3 linearity is tested using a reduce d code range: adt7518 (code 8 to 255). 4 guaranteed by design and characterization, not production tested. 5 round robin is the continuous sequential measurement of the following channels: v dd , internal temperature, ex ternal temperature (ain1, ain2), ain3, and ain4. 6 the temperature accuracy specifications ar e valid when the internal reference is not being used by the on-chip dac. for new d esigns, the adt7519 is recommended as it does not have this limitation. 7 for the amplifier output to reach its minimum voltage, the offset error must be negative. for the amplifier output to reach it s maximum voltage (v ref = v dd ), the offset plus gain error mu st be positive. 8 the sda and scl timing is measured with the inpu t filters turned on to meet the fast-mode i 2 c specification. switching off the in put filters improves the transfer rate but has a negative effect on the emc behavior of the part. 9 guaranteed by design, not production tested. 10 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ), and timed from a voltage level of 1.6 v. 11 measured with the load circuit shown in figure 4. 12 the i dd specification is valid for all dac codes and full-scale analog input voltages. interface inactive. all dacs and adcs active. l oad currents excluded.
adt7518 r e v. a | pa ge 6 o f 4 0 d a c ac c h a r ac t e r i s t i c s 1 table 2. v dd = 2.7 v to 5.5 v, r l = 4.7 k? to gnd; c l = 2 0 0 p f to g n d ; 4. 7 k ? to v dd ; all sp ecification s t min to t max , un less ot herwi s e not e d. parameter 2 min typ 3 max unit conditions/comments output voltage settling time v ref = v dd = 5 v adt7518 6 8 s 1/4 scale to 3/4 scale change (4 0h to c0h) slew rate 0.7 v/s major-code change glitch energy 12 nv-s 1 lsb change ar ound major carr y digital feedthrough 0.5 nv-s digital crossta l k 1 nv-s analog cros stal k 0.5 nv-s dac-to-dac cr osstalk 3 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p t o tal harmonic distortion C70 db v ref = 2.5 v 0.1 v p-p. frequency = 10 khz. 1 guarante e d by d e sign and characte riz a tio n , no t pro d uctio n te s t ed . 2 se e t h e s e ct ion . t e rmin olo g y 3 @ 25c. scl t 4 t 2 t 1 t 3 t 5 t 6 sda data in sda data ou t 04879-002 fi g u r e 2 . i 2 c b u s ti ming d i ag r a m t 1 t 2 t 3 t 5 t 6 t 4 t 7 t 8 d7 cs sclk din dout d6 d5 d4 d3 d2 d1 d0 x x x x x x x x x x x x xxxx d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 04879-003 f i gure 3. s p i bus t i ming d i agr a m 200 ai oh 1.6v to output pin c l 50pf 200 ai ol 04879-004 f i gur e 4 . l o a d cir c ui t fo r a c c e ss t i me a n d bus reli nqui sh t i m e 4.7k ? 4.7k ? v dd to dac o utput 200 pf 04879-005 f i gure 5. l o ad cir c uit for d a c o u tput s
adt7518 r e v. a | pa ge 7 o f 4 0 functional block diagram 7 d+/ain1 8 d?/ain2 9 ldac/ain3 14 ain4 ain4 value register ain3 value register ain2 value register ain1 value register v dd value register 12 sda 13 scl 5 gnd 6 v dd 11 add 9 ldac/ain3 3 v ref -in 4 cs address pointer register di gi tal mux di gi tal mux t high limit registers limit comparator t low limit registers v cc limit registers ain high limit registers ain low limit registers control config. 1 register control config. 2 register control config. 3 register dac configuration registers ldac configuration registers interrupt mask registers status registers on-chip temperature sensor internal temperature value register external temperature value register v dd sensor adt7518 analog mux string dac a a-to-d converter 2 dac a registers string dac b 1 dac b registers string dac c 16 dac c registers string dac d 15 v out -a v out -b v out -c v out -d int/int dac d registers power- down logic gain select logic internal reference spi/smbus interface 10 04879-006 fi g u r e 6 .
adt7518 r e v. a | pa ge 8 o f 4 0 absolute maximum ra tings table 3. p a r a m e t e r r a t i n g v dd to gnd C0.3 v to +7 v analog input voltage to gnd C0.3 v to v dd + 0.3 v digital input voltage to gnd C0.3 v to v dd + 0.3 v digital output v o ltage to gnd C0.3 v to v dd + 0.3 v reference input voltage to gnd C0.3 v to v dd + 0.3 v operating tem p erature range C40c to +120c storage temperature range C65c to +150c junction tempe r ature 150c 16-lead qsop package power dissi pati on 1 (t j max C t a )/ ja thermal imp e d a nce 2 ja junction-to- a m b i e n t 1 0 5 . 4 4 c / w jc junction-to- c a s e 3 8 . 8 c / w ir reflow soldering peak temperature 220c (0c/5c ) time at peak te mperature 10 sec to 20 sec ramp-up rate 2c/sec to 3c/sec ramp-down rat e C6c/sec table 4. i 2 c a d d r ess selection add pin i 2 c addr ess low 1001 000 float 1001 010 high 1001 011 s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . 1 va lu es re la t e t o pa cka g e bei n g use d o n a 4- la yer b o a r d. 2 junctio n-to -c as e res i s t ance is appl icab l e to co mpo n e nts fe aturing a prefer ential flow di rection, e.g., comp onents mounted o n a heat sink. junction- t o-amb ient res i s t an ce i s m o r e u s ef ul fo r a i r c ool ed pc b- m o un t e d compon en t s . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
adt7518 r e v. a | pa ge 9 o f 4 0 pin conf igura t ion and func tional descri ptions adt7518 top view (not to scale) v out -b 1 v out -c 16 v out -a 2 v out -d 15 v ref -in 3 ain4 14 cs 4 scl/sclk 13 gnd 5 sda/din 12 v dd 6 dout/add 11 d+/ain1 7 int/int 10 d? /ain2 8 ldac/ain3 9 04879-007 f i gure 7. pin config ur ation q s op ta ble 5. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic description 1 v ou t -b buffered analog output voltage from dac b. th e output amplifier has rai l -to-rail operation. 2 v ou t -a buffered analog output voltage from dac a. th e output amplifier has rai l -to-rail operation. 3 v ref -in reference input pin for all four dacs. this inp ut is buffered and has an input range from 1 v to v dd . 4 cs spi active low control input. this is the fram e synchroni z ation signal for the input data. when cs goes lo w, it ena b les the input register, and data is transferre d in on t h e rising ed ges and out on the falling ed ges of t h e subse q uent serial clocks. it is recommended that t h is pin be tied high to v dd when operating the serial interface in i 2 c mode. 5 gnd ground reference point for all circui try on the part. analog and digital ground . 6 v dd positive supply voltage, 2.7 v to 5.5 v. t h e supply should be decoupled to ground. 7 d+/ain1 d+. positive connection to ex ternal temp erature sensor. ain1. analog input. single-ended anal og input chann e l. input range is 0 v to 2.25 v or 0 v to v dd . 8 dC/ain2 dC. negative connection to ex te rnal temperatur e sensor. ain2. analog input. single-ended analog input ch anne l. input range is 0 v to 2.25 v or 0 v to v dd . 9 ldac /ain3 ldac . active low control input. transfers the contents of th e input r e gisters to their respective dac registers. a falling edge on this pin forces any or all dac registers to be upd a ted if the input registers have n e w d a ta. a minimum pulse width of 20 ns must be ap plied to the ldac pin to ensure prope r load ing of a dac register. t h is allo ws simul- taneous update of all dac outputs. bit c3 of th e control config uration 3 register enable s the ldac pin. default is with the ldac pin co ntrolling the l o a d ing of the dac registers. ain3. analog input. single-ended analog input ch anne l. input range is 0 v to 2.25 v or 0 v to v dd . 10 int/ int over limit interrupt. the output polar ity of this pin can be set to give an active low or active high interrupt when temperature,v dd , or ain limits are exceeded. the default is active low. open-dra in outputneeds a pull-up resi stor. 11 dout/add spi serial data output. logic o u t p ut. data is clocked out of any r e gister at this pin. data is cloc ke d out on the falling ed ge of sclk. open-d r ain outp utneed s a pull-up resistor. add. i 2 c serial bus address selection pin. logic input. a low on this pin give s the address 1001 000; leaving it floating gives the address 1001 010; and setting it high gives the address 1001 011. the i 2 c address set up by the add pin is not latched by the device until after this address has been sent twice. on the eig h th scl cycle of the second valid communicatio n , the serial bus a d d r ess is latche d in. any subs equent changes on this pin will have no effect on the i 2 c serial bus ad d r ess. 12 sda/din sda. i 2 c serial d a ta input/ output. i 2 c serial data to be loaded into the parts regi sters and read from these regist ers is provided on this pin. op en-drai n co nfiguration need s a pull- up resistor. din. spi serial d a ta input. seri al data to be loaded into the parts registers is pr ovi d ed on this pin. data is cloc ked into a register on the rising edge of sclk. open- d r ain configuration need s a pull- up resistor. 13 scl/sclk serial clock input. this is the clock input for the serial port. the serial c l oc k is used to clock data out of any re gister of the adt7518 an d also to clock data into any register that can be written to . ope n-drain configur ationneeds a pull- up resistor. 14 ain4 analog input. single-ended analog input channel. input range is 0 v to 2.25 v or 0 v to v dd . 15 v ou t -d buffered analog output voltage from dac d. th e output amplifier has rai l -to-rail operation. 16 v ou t -c buffered analog output voltage from dac c. th e output amplifier has rai l -to-rail operation.
adt7518 rev. a | page 10 of 40 terminology relative accuracy relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the transfer function. typical inl versus code plots can be seen in figure 10, figure 11, and figure 12. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 0.9 lsb maximum ensures monotonicity. typical dac dnl versus code plots can be seen in figure 13, figure 14, and figure 15. total unadjusted error (tue) total unadjusted error is a comprehensive specification that includes the sum of the relative accuracy error, gain error, and offset error under a specified set of conditions. offset error this is a measure of the offset error of the dac and the output amplifier (see figure 8 and figure 9). it can be negative or positive, and it is expressed in mv. offset error match this is the difference in offset error between any two channels. gain error this is a measure of the span error of the dac. it is the deviation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. gain error match this is the difference in gain error between any two channels. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. long term temperature drift this is a measure of the change in temperature error over time. it is expressed in c. the concept of long-term stability has been used for many years to describe the amount an ics parameter shifts during its lifetime. this is a concept that has typically been applied to both voltage references and monolithic temp- erature sensors. unfortunately, integrated circuits cannot be evaluated at room temperature (25c) for 10 years or so to determine this shift. manufacturers perform accelerated lifetime testing of integrated circuits by operating ics at elevated temp- eratures (between 125c and 150c) over a shorter period (typically between 500 and 1,000 hours). as a result, the lifetime of an integrated circuit is significantly accelerated due to the increase in rates of reaction within the semiconductor material. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac. it is expressed in v. reference feedthrough this is the ratio of the amplitude of the signal at the dac out- put to the reference input when the dac output is not being updated (i.e., ldac is high). it is expressed in db. channel-to-channel isolation this is the ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of another dac. it is measured in db. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011...1 to 100...00 or 100...00 to 011...11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device but is measured when the dac is not being written to. it is specified in nv-s and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s or vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s. analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping ldac high. then pulse ldac low and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv-s.
adt7518 rev. a | page 11 of 40 d a c-t o -d a c crosstalk this is t h e g l i t ch im p u ls e t r a n sfer r e d t o t h e o u t p u t o f o n e d a c d u e to a dig i t a l co de cha n ge and sub s e q ue n t ou t p ut cha n ge o f a n o t h e r d a c. t h is in cl udes b o t h dig i t a l and a n a l o g cr o sst a l k. i t is m e as ur ed b y l o adin g on e o f th e d a cs wi t h a f u l l -s cale co de c h a n g e (al l 0s t o al l 1s a nd vice v e rs a) wi th ld a c lo w a nd mon i tor i ng t h e output of anot h e r d a c . t h e e n e r g y of t h e g l itc h is exp r es s e d i n nv -s. multipl y ing ba ndwidth the am plif iers wi t h in t h e d a c ha v e a f i ni te b a n d wi d t h. t h e m u l t i p ly in g b a nd w i d t h is a m e a s ur e o f t h is. a sin e w a v e on t h e re f e re nc e ( w it h f u l l - s c a l e c o d e l o a d e d to t h e d a c ) a p p e ar s on t h e o u t p ut. th e m u l t i p l y in g b a nd w i d t h is t h e f r e q uen c y a t w h ich t h e o u t p u t a m pl i t ude fal l s t o 3 db b e lo w t h e i n p u t. t o tal ha rm oni c distor ti on this is t h e dif f er en ce b e tw e e n an ide a l si n e wa ve a nd i t s a t t e n- ua te d v e rsio n u s in g t h e d a c. t h e si n e wa ve is us e d as t h e r e fer e n c e fo r t h e d a c, an d t h e thd is a m e as u r e o f t h e ha r m o n ics p r es en t on t h e d a c o u t p ut, exp r es s e d i n db . r o un d robin this t e r m is us e d t o des c r i be t h e adt7518 c y c l in g thr o ug h t h e a v a i la b l e m e as u r em e n t cha n ne ls in s e q u ence , t a kin g a m e as ur e- m e n t on eac h cha n n e l . d a c outp ut s e ttling t i me this is t h e t i m e r e q u ir e d , fol l o w in g a p r es cr ib e d d a t a ch a n ge , fo r t h e output of a d a c to re a c h a n d re m a i n w i t h i n 0 . 5 l s b of t h e f i nal val u e . a typ i cal p r es cr ibe d c h a n g e is f r o m 1/4 s c ale t o 3/4 s c ale . amplifier footroom lower deadband codes negative offset error gain error + offset error actual output voltage negative offset error dac code ideal 04879-008 f i gure 8 . d a c t r a n s f er f u nctio n wi th nega ti v e o ffset actual gain error + offset error upper deadband codes output voltage positive offset error dac code full scale ideal 04879-009 f i gure 9 . d a c t r a n s f er f u nctio n wi th p o si ti v e o ffset ( v re f = v dd )
adt7518 rev. a | page 12 of 40 typical perf orm ance cha r acte ristics ? 0.20 ? 0.15 ? 0.10 ? 0.05 0 0.05 inl e rror (ls b ) 0.10 0.15 0.20 0 5 0 100 150 200 250 dac code 04879-010 f i gur e 1 0 . ad t7 51 8 t y pi c a l d a c inl p l o t ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 dnl e rror (ls b ) 0 5 0 100 150 200 250 dac code 04879-011 f i gur e 1 1 . ad t7 51 8 t y pi c a l d a c dnl p l o t 0.30 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v ref (v) e rror (ls b ) ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 inl wcp dnl wcp dnl wcn inl wcn 04879-012 f i gur e 1 2 . ad t7 51 8 d a c inl a n d dnl er r o r vs , v ref 0.14 ? 4 0 110 80 50 20 ?1 0 temperature ( c) e rror (ls b ) ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 dnl wcn inl wcp inl wcn dnl wcp 04879-013 f i gure 13. a d t 7 5 1 8 d a c inl e r ror and dnl e rror v s . t e mper atu r e 0 ?40 120 100 80 60 40 20 0 ?2 0 temperature ( c) e rror (ls b ) ? 1.8 ? 1.6 ? 1.4 ? 1.2 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 offset error gain error 04879-014 f i gure 14. d a c o ffs et e rror and g a i n e rror v s . t e mper ature e rror (ls b ) ?2 0 ?1 5 ?1 0 ?5 0 5 10 2.7 3.3 3.6 4.0 v dd (v) 4.5 5.0 5.5 offset error gain error v ref = 2.25v 04879-015 f i gure 15. d a c o ffs et e rror and g a i n e rror v s . v dd
adt7518 rev. a | page 13 of 40 source current sink current 2.505 dac outp ut (v ) 2.465 2.470 2.475 2.480 2.485 2.490 2.495 2.500 01 2 3 current (ma) 45 6 v dd =5 v v ref =5 v dac outp ut loade d t o m i d sca l e 04879-016 f i g u re 16. da c v ou t so ur c e an d si n k c u r r e n t c a pa b i l i ty 0 ?40 120 100 80 60 40 20 0 ?2 0 temperature ( c) e rror (ls b ) ? 1.8 ? 1.6 ? 1.4 ? 1.2 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 offset error gain error 04879-017 f i gure 17. sup p l y current v s . d a c cod e 04879-018 2.00 2.7 3.1 3.5 3.9 4.3 4.7 5.1 2.9 3.3 3.7 4.1 4.5 4.9 5.3 5.5 v cc (v) i cc (ma) 1.75 1.80 1.85 1.90 1.95 adc off dac outputs at 0v f i gure 18. sup p l y current v s . sup p ly v o ltag e @ 25 c 04879-019 7 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 v cc (v) i cc (ma) 0 1 2 3 4 5 6 f i gure 19. p o wer - d o wn cur r ent vs. su p p ly v o ltage @ 25 c 4.0 02 4 6 8 1 time ( s) dac outp ut (v ) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 04879-020 f i g u re 20. da c ha lf -s c a le s e t t l ing ( 1 / 4 to 3/ 4 s c a l e cod e c h ang e ) 1.8 dac outp ut (v ) 0.8 1.0 1.2 1.4 1.6 0.6 02 4 time ( s) 68 0.4 0.2 0 1 0 04879-021 f i g u re 21. e x it ing p o wer - d o wn to m i d s c a l e
adt7518 rev. a | page 14 of 40 0.4700 0 2 468 1 time ( s) dac outp ut (v ) 0.4650 0.4655 0.4660 0.4665 0.4670 0.4675 0.4680 0.4685 0.4690 0.4695 0 04879-022 f i gur e 2 2 . ad t7 51 8 d a c m a j o r co de t r a n si t i o n gli t ch ene r gy ; 0... 11 to 1 00. ..0 0 0.4730 02 4 6 8 1 0 time ( s) dac outp ut (v ) 0.4685 0.4690 0.4695 0.4700 0.4705 0.4710 0.4715 0.4720 0.4725 04879-023 f i gure 23. a d t 7 5 1 8 d a c m a j o r cod e t r a n s i ti on g litch e n er gy ; 10 0 00 to 0 1 1 1 1 0 full-s cale e rror (mv ) ?12 ?10 ?8 ?6 ?4 ?2 12 3 v ref (v) 45 v dd =5 v t a =2 5 c 04879-024 f i gure 24. d a c f u l l - s c a l e e rror v s . v re f 2.329 01 2 3 4 time ( s) 2.322 2.323 2.324 2.325 2.326 2.327 2.328 5 v dd = 5v v ref = 5v dac output loaded to midscale 04879-025 dac outp ut (v ) f i gure 25. d a c-to -d a c crosstalk 04879-026 1.0 0 200 400 600 800 1000 adc code inl e rror (ls b ) ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 f i g u re 26. a d c inl wit h r e f = v dd (3. 3 v ) 04879-027 ?1 0 ac p s rr (db) ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 0 1 1 0 100 frequency (khz) 100mv ripple on v cc v ref = 2.25v v dd = 3.3v temperature = 25 c f i g u r e 2 7 . p s r r v s . s u pp l y r i pp le f r e q u e n c y
adt7518 rev. a | page 15 of 40 04879-028 temperature ( c) ?30 0 40 85 120 1.5 te mp e rature e rror ( c) ? 1.0 ? 0.5 0 0.5 1.0 e x te rnal te mp era t ure @ 3 .3 v i n te r n a l t em pe ra tu re @ 5 v inte rnal te mp era t ure @ 3 .3 v e x te rnal te mp era t ure @ 5 v f i g u re 28. inte rn al t e m p er at ure e r r o r @ 3. 3 v and 5 v 04879-029 e rror (ls b ) ?1 0 1 2 3 ?2 ?3 ?4 v dd =3 . 3 v ?40 ? 20 0 temperature ( c) 20 40 60 80 100 120 gain er ror off s et err o r f i gure 29. a d c o ffs et e rror and g a i n e rror v s . t e mper ature 04879-030 v dd (v) e rror (ls b ) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 ?3 ?2 ?1 0 1 2 3 offset error gain error f i gure 30. a d c o ffs et e rror and g a i n e rror v s . v dd 04879-031 15 te mp e rature e rror ( c) ?1 0 ?5 0 5 10 ?1 5 ?2 0 ?2 5 01 0 2 0 pcb leakage resistance (m ? ) 30 40 50 60 70 80 90 100 v dd =3 . 3 v te mp era t ure = 2 5 c d+ to gnd d+ to v cc f i g u re 31. e x ter n a l t e m p er at ure e r r o r v s . pcb l e ak ag e r e s i s t anc e 04879-032 te mp e rature e rror ( c) ?60 ?50 ?40 ?30 ?20 ?10 0 v dd =3 . 3 v 0 5 10 15 20 25 capacitance (nf) 30 35 40 45 50 f i gure 32. e x ter n a l t e m p er ature e r r o r v s . capacit a nce be t w een d+ and d C 04879-033 10 te mp e rature e rror ( c) 0 2 4 6 8 ?2 ?4 ?6 noise frequency (hz) v dd = 3.3v common-mode voltage = 100mv 1 100 200 300 400 500 600 f i gure 33. e x ter n a l t e m p er ature e r r o r v s . com m on-m ode no ise f r equ e nc y
adt7518 rev. a | page 16 of 40 04879-034 70 te mp e rature e rror ( c) 20 30 40 50 60 10 0 ?10 1 100 200 noise frequency (mhz) 300 400 500 600 v dd = 3.3v differential-mode voltage = 100mv f i gure 34. e x ter n a l t e m p er ature e r r o r v s . d i ffer e nti a l-m o de n o ise f r equenc y 04879-035 noise frequency (hz) 250mv v dd = 3.3v 1 100 200 300 400 500 600 0.6 temperature error ( c) ?0.4 ?0.2 0 0.2 0.4 ?0.6 f i gure 35. inte rn al t e m p er ature e r r o r v s . p o wer sup p l y n o is e f r equenc y 04879-036 140 te mp e rature ( c) 40 60 80 100 120 20 0 10 20 time (s) 30 40 50 0 60 external temperature t e m p e r a t u r e o f e n v i r o n m e n t c h a n g e d h e r e internal temperature f i gur e 3 6 . t e m p er atur e se nsor re spo n se t o ther ma l sho c k 0 atte nuation (db) ?2 5 ?2 0 ?1 5 ?1 0 ?5 1 10 100 1k 10k 100k 1m 10m frequency (hz) 04879-037 f i g u re 37. da c m u l t iply ing band widt h (small s i gnal f r eq uenc y resp ons e )
adt7518 rev. a | page 17 of 40 theory of operation directly after the power-up calibration routine, the adt7518 goes into idle mode. in this mode, the device is not performing any measurements and is fully powered up. all four dac outputs are at 0 v. to begin monitoring, write to the control configuration 1 register (address 18h) and set bit c0 = 1. the adt7518 goes into its power-up default measurement mode, which is round robin. the device then to take measurements on the v dd chan- nel, internal temperature sensor channel, external temperature sensor channel, or ain1 and ain2, ain3, and finally ain4. once it finishes taking measurements on the ain4 channel, the device immediately loops back to start taking measurements on the v dd channel and repeats the same cycle as before. this loop continues until the monitoring is stopped by resetting bit c0 of the control configuration 1 register to 0. it is also possible to continue monitoring as well as switching to single-channel mode by writing to the control configuration 2 register (address 19h) and setting bit c4 = 1. further explanation of the single-channel and round robin measurement modes is given in later sections. all measurement channels have averaging enabled on them on power-up. averaging forces the device to take an average of 16 readings before giving a final measured result. to disable aver- aging and consequently decrease the conversion time by a factor of 16, set bit c5 = 1 in the control configuration 2 register. there are four single-ended analog input channels on the adt7518: ain1 to ain4. ain1 and ain2 are multiplexed with the external temperature sensor terminals d+ and dC. bits c1 and c2 of the control configuration 1 register (address 18h) are used to select between ain1/ain2 and the external temperature sensor. the input range on the analog input channels is dependent on whether the adc reference used is the internal v ref or v dd . to meet linearity specifications, it is recommended that the maximum v dd value is 5 v. bit c4 of the control configuration 3 register is used to select between the internal reference or v dd as the analog inputs adc reference. controlling the dac outputs can be done by writing to the dacs msb and lsb registers (addresses 10h to 17h). the power-up default setting is to have a low going pulse on the ldac pin (pin 9) controlling the updating of the dac outputs from the dac registers. alternatively, one can configure the updating of the dac outputs to be controlled by means other than the ldac pin by setting bit c3 = 1 of the control config- uration 3 register (address 1ah). the dac configuration register (address 1bh) and the ldac configuration register (address 1ch) can now be used to control the dac updating. these two registers also control the output range of the dacs and selecting between the internal or external reference. dac a and dac b outputs can be configured to give a voltage output proportional to the temperature of the internal and external temperature sensors, respectively. the dual serial interface defaults to the i 2 c protocol on power- up. to select and lock in the spi protocol, follow the selection process as described in the serial interface selection section. the i 2 c protocol cannot be locked in, while the spi protocol is automatically locked in on selection. the interface can be switched back to be i 2 c on selection when the device is powered off and on. when using i 2 c, the cs pin should be tied to either v dd or gnd. there are a number of different operating modes on the adt7518 devices and all of them can be controlled by the configuration registers. these features consist of enabling and disabling interrupts, polarity of the int/ int pin, enabling and disabling the averaging on the measurement channels smbus timeout and software reset. power-up calibration it is recommended that no communication to the part be ini- tiated until approximately 5 ms after v dd has settled to within 10% of its final value. it is generally accepted that most systems take a maximum of 50 ms to power up. power-up time is directly related to the amount of decoupling on the voltage supply line. during the 5 ms after v dd has settled, the part is performing a calibration routine. any communication to the device during calibration will interrupt this routine, and could cause erro- neous temperature measurements. if it is not possible to have v dd at its nominal value by the time 50 ms has elapsed or if communication to the device has started prior to v dd settling, it is recommended that a measurement be taken on the v dd chan- nel before a temperature measurement is taken. the v dd measurement is used to calibrate out any temperature measure- ment error due to different supply voltage values. conversion speed the internal oscillator circuit used by the adc has the capa- bility to output two different clock frequencies. this means that the adc is capable of running at two different speeds when doing a conversion on a measurement channel. thus, the time taken to perform a conversion on a channel can be reduced by setting bit c0 of the control configuration 3 register (address 1ah). this increases the adc clock speed from 1.4 khz to 22 khz. at the higher clock speed, the analog filters on the d+ and dC input pins (external temperature sensor) are switched off. this is why the power-up default setting is to have the adc working at the slow speed. the typical times for fast and slow adc speeds are given in the specifications.
adt7518 rev. a | page 18 of 40 the ad t7518 p o w e rs u p wi t h a v era g in g o n . this m e a n s ev er y ch an nel i s me a s u r e d 1 6 t i me s a n d i n te r n a l ly a v e r age d to re d u c e n o is e . th e con versio n tim e c a n als o be s p ed u p b y t u r n in g o f f t h e a v era g i n g. t h is is do ne b y s e t t in g bi t c5 o f t h e c o n t r o l c o nf igur a t io n 2 r e g i ster (a ddr e s s 19h) to 1. func ti on descript io n v o l t a g e outpu t digital-t o - a n alo g con v er t e rs the ad t7518 has f o ur r e sis t o r s t r i n g d a cs fab r ica t ed on a cm os p r o c es s wi t h r e s o l u tio n s o f 12, 10, a n d 8 b i ts, r e s p ec- t i vely . t h e y c o n t ai n fou r output b u f f e r am pl i f i e rs and are w r it te n to v i a i 2 c se ri al in t e rf a c e o r s p i se ri al in t e rf a c e . see th e s e ri al i n t e rfa c e secti o n f o r m o r e i n f o rm a t io n . the ad t7518 op era t es f r o m a sin g le s u p p l y o f 2.7 v t o 5.5 v , a nd t h e o u t p u t b u f f er a m plif iers p r o v ide ra i l - t o-ra i l o u t p u t swin g wi t h a s l e w ra t e o f 0.7 v/s. al l f o ur d a cs s h a r e a com- mo n re f e re nc e i n put , v ref -i n. th e r e fer e nce i n pu t is b u f f er e d t o dra w vir t ual l y no c u r r en t f r o m th e r e fer e nce s o ur ce b e c a us e i t o f fers t h e s o ur ce a hig h i m p e dan c e in pu t. th e de vices ha v e a p o w e r - do w n mo de i n w h ich a l l d a cs m a y b e tur n e d o f f co m p letely w i t h a hig h im p e dance o u t p u t . e a c h d a c o u t p u t wil l n o t b e u p da ted u n til i t r e cei v es t h e ld a c co mmand . th er efo r e , w h i l e t h e d a c r e g i s t ers w o u l d ha v e b e e n wr i t ten t o wi t h a ne w va l u e , t h is va lue wi l l n o t b e r e p r es en t e d b y a v o l t a g e o u t p u t un t i l t h e d a cs ha v e r e ceiv e d t h e l d a c co m m a n d . r e adi n g b a ck f r o m an y d a c r e g i st er p r ior to issu ing an l d a c c o m m and wi l l re su lt in t h e dig i t a l val u e t h a t co r r es p o n d s t o t h e d a c o u t p ut v o l t ag e . th us, t h e dig i t a l val u e wr i t t e n t o t h e d a c r e g i s t er ca nn ot b e r e ad b a ck un t i l a f t e r t h e l d a c co mman d has b e en i n i t i a te d . this l d a c co mman d can b e g i ven b y ei t h e r p u l l in g t h e ld a c pi n l o w (fal lin g edg e lo ads d a cs), s e t t in g u p b i ts d4 and d5 o f th e d a c co nf igura t io n r e g i st er (a d d r e ss 1bh), o r usin g t h e ld a c r e g i ster (a ddr ess 1c h). wh e n u s i n g t h e ld a c pi n to c o n t ro l t h e d a c re g i st e r l o a d i n g , th e lo w g o in g p u ls e wid t h sh o u ld be 20 n s minim u m. the ld a c p i n has to go hi g h an d lo w a g ai n b e fo r e t h e d a c re g i ste r s c a n b e rel o a d e d . digital-t o - a n alog s e c t ion t h e arch ite c tu re of one d a c c h an nel c o ns i s t s of a re s i stor s t r i n g d a c f o l l o w ed b y a n o u t p u t b u f f er a m p l if ier . th e v o l t a g e at t h e v ref - i n pi n or t h e on - c h i p re f e re nc e of 2 . 2 5 v prov i d e s t h e r e fer e n c e v o l t a g e fo r t h e co r r es p o ndin g d a c. f i gur e 38 s h o w s a b l o c k dia g ram o f t h e d a c a r chi t e c t u r e . sin c e t h e in pu t co din g t o t h e d a c is st ra ig h t b i na r y , t h e ide a l ou t p ut v o l t a g e is gi v e n b y n ref out d v v 2 = w h er e: d = decimal eq ui valen t o f t h e b i na r y co de tha t is lo aded t o t h e da c r e g i s t e r : 0 t o 255 f o r ad t7518 (8 b i ts) n = d a c re s o lut i on r e sist or stri ng t h e re s i stor st r i ng s e c t i o n i s s h ow n i n f i g u re 3 9 . i t i s s i m p ly a s t r i n g o f r e sis t o r s, eac h o f a p p r o x ima t e l y 603 ?. th e dig i tal co de lo ade d to t h e d a c r e g i ster deter m i n es a t w h ich no de on t h e s t r i ng t h e vol t a g e is t a p p e d o f f t o b e fe d in to t h e o u t p u t a m plif ier . th e vol t a g e is t a p p e d o f f b y closin g o n e o f t h e swi t ch es co nnec tin g t h e s t r i n g to th e am p l if ier . b e ca us e i t is a s t r i n g o f r e sis t o r s, i t is gua r a n t e ed m o n o t o nic. input register dac register resistor string v out -a output buffer amplifier gain mode (gain = 1 or 2) reference buffer int v ref v ref -in 04879-038 f i gure 38. sing le da c chann e l a r ch itectur e r r r r r to output amplifier 04879-039 f i gur e 3 9 . resi st or str i ng string dac a 2.25v internal v ref v ref -in string dac b string dac c string dac d 04879-040 f i gure 40. d a c r e f e r e nc e buffer c i rcui t
adt7518 rev. a | page 19 of 40 d a c r e fe ren c e inputs v ref a nd this can b e in cr eas e d to 0 v t o 2 v ref . i n cr easing the output volt ag e s p an to 2 v ref can b e don e b y s e t t in g d0 = 1 f o r d a c a (i n t er na l t e m p era t ur e s e n s o r ) a nd d1 = 1 fo r d a c b (ext er nal t e m p e r a t ur e s e n s o r ) i n t h e d a c conf igura t io n r e g i s t er (a ddr ess 1bh). ther e is a n in pu t r e fer e n c e pin fo r t h e d a cs. this r e fer e n c e in p u t is b u f f er ed (s ee f i gur e 40 ). the ad v a n t a g e wi t h t h e b u f f er e d in p u t is t h e hi g h im p e dan c e i t p r es en ts t o t h e v o l t a g e s o ur ce dr i v in g i t . th e us er ca n ha v e an exter n a l r e fer e n c e vol t a g e as lo w as 1 v and as hig h as v dd . t h e re st r i c t i o n of 1 v i s d u e to t h e f o ot ro om of t h e re f e re nc e bu f f e r . the o u t p u t v o l t a g e is c a p a b l e o f t r ackin g a maxi m u m t e m p - era t ur e ra n g e o f C128c t o +12 7 c, b u t t h e def a u l t s e t t in g is C40c t o +127c. i f th e o u t p u t v o l t a g e ra n g e is 0 v t o v ref -in (v ref -in = 2.25 v), t h en t h is cor r es p o n d s t o 0 v r e p r es en t i n g C40c, an d 1.48 v r e p r es en tin g +127c. this, o f co urs e , wil l g i v e a n u p p e r dead b a nd betw een 1.48 v an d v re f . the ld a c co nf igura t io n r e g i s t er con t r o ls th e o p tio n to s e lec t b e tw e e n i n t e r n a l a nd ext e r n al vol t a g e r e fer e n c e s . th e defa u l t s e t t i n g is fo r ex ter n a l r e fer e nc e s e le c t e d . output a m plifi e r the i n t e r n al and ext e r n al a n alog t e m p era t ur e of fs et r e g i s t ers ca n be us e d t o va r y this u p p e r dead b a nd and , con s eq uen t l y , th e t e m p era t ur e t h a t 0 v co r r es p o nds t o . t a b l e 6 and t a b l e 7 g i ve exa m ples o f h o w t h is is don e u s in g a d a c o u t p u t v o l t a g e sp an of v ref a nd 2 v re f , r e s p e c t i v e ly . sim p ly wr i t e i n t h e tem p era t ur e val u e , in tw os c o m p lem e n t f o rma t , a t w h ic h 0 v is t o s t a r t. f o r exa m p l e , if usin g th e d a c a o u t p u t an d 0 v t o s t a r t a t C40c, p r og ra m d8h i n t o t h e i n t e r n al a n alog t e m p era t ur e o f fs et r e g- ist e r (a ddr ess 2 1 h). this is an 8-b i t r e g i ster a n d has a t e m p - e r a t u r e of f s e t re s o lut i on of on ly 1 c f o r a l l d e v i c e m o d e l s . u s e t h e fo r m u l as fol l o w in g t h e t a b l es t o det e r m i n e t h e va l u e t o p r og ra m in t o t h e o f fs et r e g i s t ers. the o u t p u t b u f f er a m plif ier can g e n e r a t e o u t p ut v o l t a g es t o wi t h in 1 mv o f ei t h er ra i l . i t s ac t u al ran g e de p e n d s on t h e val u e of v ref , g a i n , a n d of f s e t e r ror . i f a ga in o f 1 is s e lec t e d (b i t s 0 t o 3 o f th e d a c co nf igura t io n r e g i s t er = 0), th e o u t p u t ra n g e is 0.001 v t o v ref . i f a ga in o f 2 is s e lec t e d (b i t s 0 t o 3 o f th e d a c co nf igura t io n r e g i s t er = 1), th e o u t p u t ra n g e is 0.001 v t o 2 v ref . b e c a u s e o f cl am pi ng , how e ve r , t h e max i m u m output i s l i mite d to v dd ? 0.001 v . the o u t p u t am plif ier ca n dr i v e a lo ad o f 4.7 k? t o gnd o r v dd , in p a ral l e l wi t h 200 pf t o gnd o r v dd (s ee f i gur e 5). th e s o ur ce a nd sin k ca p a b i li ties o f t h e o u t p u t am p l if ier ca n be s een i n t h e pl ot of f i g u re 1 6 . table 6. therm a l voltage out p ut (0 v to v ref ) o / p vo ltage (v) defau l t c max c sample c 0 C40 C128 0 0.5 +17 C71 +56 1 +73 C15 +113 1.12 +87 C1 +127 1.47 +127 +39 udb ? 1.5 udb ? +42 udb ? 2 udb ? +99 udb ? 2.25 udb ? +127 udb ? the s l e w ra t e is 0.7 v/s wi t h a half-s cale s e t t lin g tim e t o 0.5 ls b (a t 8 b i ts) o f 6 s. thermal v o lta ge o u tput the ad t7518 c a n o u t p u t v o l t ag es tha t a r e p r op o r tio n al t o t e m p era t ur e . d a c a o u t p u t can b e co nf igur ed t o r e p r es en t t h e t e m p era t ur e o f t h e i n t e r n al s e ns o r w h i l e d a c b o u t p ut can b e co nf igur e d t o r e p r es en t t h e ext e r n al t e m p er a t ure s e n s o r . bi ts c5 a nd c6 o f t h e c o n t r o l c o nf igur a t io n 3 r e g i ster s e le c t t h e te m p - e r a t u r e prop or t i on a l output vo lt age. e a ch t i m e a te m p e r atu r e m e as ur e m en t is t a k e n, t h e d a c o u t p u t is u p da te d . th e o u t p ut r e s o l u tio n f o r th e adt7518 is 8 b i ts wi th a 1c c h a n g e co r r es- p o n d i ng to 1 l s b ch ange. t h e d e f a u l t output r a nge i s 0 v to ? uppe r de ad band has be e n re ache d . da c o u tput is no t capabl e of increasing. see fig . u r e 9 c1 d+ low-pass filter f c = 65khz bias diode v dd to adc v out+ v out? remote sensing transistor (2n3906) optional capacitor, up to 3nf max. can be added to improve high frequency noise rejection in noisy environments d? i n i i bias 04879-041 f i g u re 41. sig n al condit ion i ng f o r e x t e rn al d i ode t e mpe r at ure s e ns o r
adt7518 rev. a | page 20 of 40 bias diode internal sense transistor v dd to adc v out+ v out ? i n i i bias 04879-042 f i g u re 42. t o p l e ve l st ruc t u r e of in ter n al t e mpe r at u r e s e n s or table 7. therm a l voltage out p ut (0 v to 2 v re f ) o / p vo ltage (v) defau l t c max c sample c 0 C40 C128 0 0.25 C26 C114 +14 0.5 +12 C100 +28 0.75 +3 C85 +43 1 +17 C71 +57 1.12 +23 C65 +63 1.47 +43 C45 +83 1.5 +45 C43 +85 2 +73 C15 +113 2.25 +88 0 +127 2.5 +102 +14 udb* 2.75 +116 +28 udb* 3 udb* +42 udb* 3.25 udb* +56 udb* 3.5 udb* +70 udb* 3.75 udb* +85 udb* 4 udb* +99 udb* 4.25 udb* +113 udb* 4.5 udb* +127 udb* * u p p e r de ad b a n d h as b e en r e ac h e d . d a c o u t p u t is n o t ca p a ble o f in cr e asin g . s e e f igu r e 9. n e g a t i ve te m p e r a t u r e s : () ( ) 128 0 re + = w h er e: d7 o f of fs et reg i s t er c o de is s e t t o 1 f o r n e ga t i v e t e m p era t ur es . ex a m p l e : ( ) () 58h d 88 128 40 d re = = + ? = sin c e a nega t i ve t e m p era t ur e has b e e n ins e r t e d in t o t h e e q u a t i on , db 7 ( m sb ) of t h e of f s e t re g i ste r c o d e i s s e t to 1 . ther efo r e 58h b e co m e s d8h. 58h + d b 7(1) = d8h p o s i t i ve te m p e r a t u r e s : of f s e t re gis t e r co d e (d) = 0 v t e m p ex a m p l e : of f s e t re gis t e r co d e (d) = 10d = 0ah t h e f o l l ow i n g e q u a t i on i s u s e d to wor k out t h e v a r i ou s t e m p era t ur es fo r t h e co r r es p o ndin g 8- b i t d a c o u t p ut: ( ) ( ) 0 1 / 8 + = f o r exa m ple , if th e o u t p ut is 1.5 v , v ref -in = 2.2 5 v , 8-b i t d a c has a n l s b size = 2.25 v/256 = 8.79 x 10 C3 , a nd 0 v t e m p era t ur e is a t C128c, th en the r e s u l t an t tem p er a t ur e is ( ) () + = ? + ? 43 128 10 79 . 8 5 . 1 3 f i g u re 4 3 show s a g r a p h of t h e d a c output ve r s u s te m p e r atu r e fo r a v ref -in = 2.25 v . temperature ( c) dac outp ut (v ) 0 0.15 ?128 ?110 ? 9 0 ? 70 ?50 ? 30 ? 1 0 1 0 3 0 5 0 7 0 9 0 110 127 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 1.65 1.80 1.95 2.10 2.25 0v = ? 128 c 0v = ? 40 c 0v = 0 c 04879-043 f i g u re 43. da c o u t p ut v s . t e mpe r at u r e v ref -in = 2. 25 v func ti on a l descripti o nanal og in pu t s single-ende d inputs the ad t7518 of f e rs f o u r sin g le-ende d a n alog in p u t c h a n n e ls. the a n alog in p u t ra n g e is f r o m 0 v t o 2.25 v , o r 0 v t o v dd . t o ma in t a i n t h e li ne a r i t y sp e c if ica t io n, i t is r e com m e n d e d t h a t t h e max i m u m v dd val u e b e s e t a t 5 v . s e le c t ion b e t w e e n t h e tw o in p u t ra n g es is do ne b y bi t c4 o f t h e c o n t r o l c o nf igura t io n 3 r e g i s t er (a ddr ess 1a h). s e t t in g t h is b i t t o 0 s e ts u p t h e a n alog i n put a d c re f e re nc e to b e s o u r c e d f rom t h e i n t e r n a l vo lt age r e f e r e n c e o f 2.25 v . s e t t in g t h e b i t t o 1 s e ts u p t h e ad c re f e re nc e to b e s o u r c e d f rom v dd .
adt7518 rev. a | page 21 of 40 the a d c r e s o lu t i o n is 10 b i ts a nd is m o st ly sui t a b le fo r dc i n pu t s i g n a l s . bit s c 1 : 2 of t h e c o n t ro l c o n f i g u r a t i o n 1 re g i ste r (a ddr es s 18h) ar e us ed t o s e t u p p i n s 7 an d 8 as ain1 an d a i n 2 . f i g u re 4 4 show s t h e ove r a l l v i e w of t h e 4 - ch an nel an a l o g in p u t p a t h . adc tr ans f er func tion the o u t p u t co din g o f th e adt7 518 a n alog in p u ts is s t ra ig h t b i na r y . t h e desi g n e d co de t r a n s i t i o n s o c c u r mi d w a y b e tw e e n s u cces s i v e in teger ls b val u es (i . e ., 1/2 ls b , 3/2 ls b). the ls b is v dd /1024 o r in ter n al v ref /1024, in t e r n al v ref = 2.25 v . the idea l t r a n sfer cha r ac t e r i st ic is sh o w n in f i gur e 47. m u l t i p l e x e r 10-bit adc to adc value register ain1 ain2 ain3 ain4 04879-044 111...111 111...110 111...000 011...111 +v ref ? 1lsb 0v 1/2lsb analog input adc code 1lsb = int v ref /1024 1lsb = v dd /1024 000...010 000...001 000...000 04879-047 f i g u re 44. q u ad a n al og input p a t h c o n v er t e r o p er at io n the a n alog in pu t cha n n e ls us e a s u cces s i v e a ppr o x ima t ion a d c b a s e d on a c a p a c i tor d a c . f i g u re 4 5 an d f i g u re 4 6 show sim p lif i ed s c h e ma tics o f t h e ad c. f i gur e 45 sh o w s the ad c d u r i n g acq u isi t i o n phas e. sw2 i s clos e d an d s w 1 is i n p o si t i on a. the com p a r a t o r is h e l d in a b a lan c e d con d i t io n an d t h e s a m p ling c a p a ci t o r acq u ir es the sig n al o n ai n. f i gure 47. sing le -ended t r ansfe r f u nc tion t o work out t h e volt age on a n y an a l o g i n put ch an n e l, t h e f o l l o w in g m e t h o d can be us e d : control logic cap dac acquisition phase sampling capacitor comparator int v ref ref v dd a in sw1 a b sw2 ref/2 04879-045 1 ls b = re f e re n c e (v)/1024 c o n v er t t h e value r e ad b a ck f r om t h e ai n val u e r e g i s t er i n t o a de cima l fo r m a t . () = d = decimal ex a m p l e : f i g u re 45. a d c ac quis it i o n p h as e control logic cap dac conversion phase sampling capacitor comparator int v ref ref v dd a in sw1 a b sw2 ref/2 04879-046 i n te r n a l re f e re n c e u s e d . t h e r e f ore v ref = 2.25 v . ain va l u e = 512d 3 10 197 . 2 1024 / 25 . 2 1 ? = = v voltage ain 125 . 1 10 197 . 2 512 3 = = ? analog i n pu t esd p r ot ec tio n f i g u re 4 8 show s t h e i n put st r u c t u r e on a n y of t h e an a l o g i n put pi ns t h a t prov i d e s e s d prote c t i on . t h e d i o d e prov i d e s t h e m a i n es d p r o t ecti o n f o r th e a n alog i n p u t s . c a r e m u s t be ta k e n tha t th e a n alog i n p u t si gn al n e v e r d r o p s be lo w t h e gn d ra il b y m o r e than 200 mv . i f this ha p p en s, th e dio d e wil l become fo r w a r d-b i as e d a nd st a r t co nd u c t i n g c u r r en t in to t h e subst r a t e. the 4 pf ca p a c i t o r is th e typ i cal p i n c a p a c i tan c e a nd t h e r e sis t o r is a l u m p e d com p on e n t made u p o f t h e o n -r esis t a n c e o f t h e m u lt ip l e x e r s w it c h . f i g u re 46. a d c co nvers i on p h as e w h en t h e ad c e v en t u al ly g o es in t o con v ersio n phas e (s e e f i gur e 46), sw2 o p en s and sw1 m o v e s t o p o si tio n b , c a usin g th e com p a r a t o r t o become un ba lan c e d . th e con t r o l log i c a n d t h e d a c a r e us e d to ad d and sub t r a c t f i xe d am o u n t s o f cha r ge f r o m th e s a m p lin g ca p a c i t o r t o b r in g t h e com p a r a t o r back in t o a balanced condi t io n. w h en t h e co m p a r a t o r is r e balan c e d , the co n v ersio n is com p let e . the co n t r o l log i c g e n e ra t e s th e ad c output c o d e . f i g u re 4 7 show s t h e a d c t r ans f e r f u nc t i o n f o r t h e an a l o g i n put s . 4pf a in 100 ? 04879-048 f i g u re 48. equiv a le nt a n al og input e s d ci r c u i t
adt7518 rev. a | page 22 of 40 watchdog limit comparisons interrupt mask registers control configuration register 1 interrupt status register (temp and ain1 to ain4) interrupt status register 2 (v dd ) s t atus bits s t atus bit read reset s/w reset internal temp int/int (latched output) int/int enable bit external temp v dd diode fault ain1? ain4 04879-049 f i gure 49. inte rrupt struc t ure ain int e r r u p ts the m e as ur e d r e s u l t s f r o m t h e ain i n p u ts a r e co m p a r e d w i t h th e a i n v hi g h (g r e a t er tha n com p a r is o n ) an d v lo w (les s tha n o r e q ua l t o com p ar is o n ) limi ts. a n in t e r r u p t o c c u rs if t h e ai n in p u ts exce e d or e q ual t h e limi t r e g i s t ers. th es e v o l t a g e limi ts a r e s t o r e d in on-chi p r e g i st ers. n o t e t h a t t h e li mi t r e g i st ers a r e 8 b i ts lo n g while th e ai n con v ersio n r e s u l t is 10 b i ts lo n g . i f the v o l t a g e li mi ts a r e n o t mask e d ou t, t h e n an y o u t - o f -limi t com- pa ri so n s g e n e ra t e f l a g s tha t a r e s t o r e d in th e i n t e rr u p t s t a t u s 1 re g i ste r ( a d d r e s s = 0 0 h ) an d o n e or more out - o f - l i m it re su lt s wi l l c a us e t h e i n t/ int o u t p u t t o p u l l ei th er hig h or lo w dep e n d in g on th e o u t p u t p o la r i ty s e t t ing. i t is g o o d desig n p r ac tice t o mask o u t in t e r r u p ts f o r c h a n n e ls tha t a r e o f n o co n c er n t o t h e a p plica t io n. f i gu r e 49 s h o w s t h e in t e r r u p t s t r u c t ur e f o r th e adt7518. i t g i v e s a b l o c k diag ra m r e p r e s e n ta ti o n o f h o w th e va ri o u s m e a s ur em en t c h a n n e ls a f f e ct th e in t/ int pi n . func ti on a l descripti o nme as urement te m p e r a t u r e s e n s o r the ad t7518 c o n t a i n s an ad c wi t h sp ecial in p u t sig n al co ndi t i onin g to ena b le o p er a t ion w i t h ex ter n a l a nd o n -chi p dio d e t e m p era t ur e s e n s o r s. w h en t h e a d t751 8 is o p era t i n g in sin g le-cha nne l m o de , t h e a d c co n t i n ual l y p r o c es s e s t h e m e a s ur e m en t t a k e n o n on e ch annel o n ly . this cha n n e l is p r es e l e c t e d b y bi ts c0: c 2 in t h e c o n t r o l c o nf igura t io n 2 re g i ste r ( a d d r e s s 1 9 h ) . w h e n i n rou nd ro bi n m o d e , t h e an a l o g in p u t m u l t i p lexer s e q u en t i al l y s e lec t s t h e v dd in p u t cha n ne l, t h e on- c h i p te m p e r a t u r e s e ns or to me a s u r e i t s i n te r n a l te m p e r a t u r e, ei t h er t h e exter n al t e m p era t ur e s e n s o r o r ai n1 a nd ai n2, ain3, an d t h e n ain4. th es e sig n als a r e dig i t i ze d b y t h e ad c an d t h e re su lt s are store d i n t h e v a r i ou s v a lu e re g i ste r s . the m e as ur e d r e s u l t s f r o m t h e tem p er a t ur e s e ns o r s a r e co m- p a r e d w i t h t h e i n ter n a l an d ex te r n a l t hi g h , t lo w limi ts. th es e t e m p era t ur e limi ts a r e st o r e d i n o n -chi p r e g i s t ers. i f t h e t e m p - era t ur e li mi ts a r e n o t mask e d , an y o u t-o f -limi t co m p a r is o n s g e n e r a t e f l a g s t h a t a r e st o r e d in t h e i n t e r r u p t s t a t us 1 r e g i st er . o n e or more out - of - l i m it re su lt s w i l l c a u s e t h e i n t / int output t o p u l l ei ther hig h o r lo w dep e ndin g on the o u t p u t p o la r i ty se t t in g . theo r e tical l y , the t e m p era t ur e m e as ur in g cir c ui t can m e as ur e t e m p era t ur es f r o m C128c t o +127c wi th a r e s o l u tio n o f 0.25c. h o w e v e r , t e m p era t ur es o u tside t a a r e o u tside t h e gua r a n te e d o p e r a t in g tem p era t ur e ra n g e o f t h e de vice . t e m p - era t ur e m e as ur em en t f r o m C12 8 c t o +127c is p o s s i b le usin g an e x te r n a l s e ns or . t e m p er a t ur e me as ur emen t is i n i t ia t e d b y t h r e e m e t h o d s. th e f i rst m e t h o d is a p plica b le w h en t h e p a r t is in si ng le-cha n n e l m e as ur e m en t m o de . th e tem p era t ur e is me as ur e d 16 t i m e s and in t e r n al l y a v erag ed t o r e d u c e no is e . i n sin g le-cha nn e l m o de , th e p a r t is co n t in uous l y m o ni t o r i n g th e s e lec t e d c h a nne l , i . e . , as s o o n as one m e as ur emen t is t a k e n an o t h e r o n e is s t a r t e d o n t h e s a me cha n ne l. th e t o t a l t i me t o m e as ur e a t e m p era t ur e chann e l wi t h t h e ad c op era t in g a t s l o w s p ee d is typ i cal l y 11.4 m s (712 s 16) f o r th e in t e r n al t e m p er a t ur e s e n s o r a n d 24 .22 m s (1.51 m s 16) f o r t h e ext e r n al tem p er a t ur e s e ns o r . th e ne w te m p e r atu r e v a lu e i s store d i n t w o 8 - bit re g i ste r s and i s re a d y fo r r e ading b y t h e i 2 c or spi i n te r f a c e. t h e u s e r h a s t h e opt i on o f dis a b l in g t h e a v era g in g b y s e t t in g b i t 5 in t h e c o n t r o l c o nf igura t io n 2 r e g i s t er (a ddr es s 19h). th e adt7518 def a u l ts o n p o w e r - u p w i t h a v er a g in g ena b le d .
adt7518 rev. a | page 23 of 40 the second method is applicable when the part is in round robin measurement mode. the part measures both the internal and external temperature sensors as it cycles through all pos- sible measurement channels. the two temperature channels are measured each time the part runs a round robin sequence. in round robin mode, the part continuously measures all channels. temperature measurement is also initiated after every read or write to the part when the part is in either single-channel measurement mode or round robin measurement mode. once serial communication has started, any conversion in progress is stopped and the adc is reset. conversion starts again immediately after the serial communication has finished. the temperature measurement proceeds normally as described in the preceding section. v dd monitoring the adt7518 also has the ability to monitor its own power supply. the part measures the voltage on its v dd pin to a resolution of 10 bits. the resulting value is stored in two 8-bit registers; the two lsbs are stored in register address 03h and the eight msbs are stored in register address 06h. this allows the option of doing just a 1-byte read if 10-bit resolution is not important. the measured result is compared with the v high and v low limits. if the v dd interrupt is not masked, any out-of-limit comparison generates a flag in the interrupt status 2 register and one or more out-of-limit results will cause the int/ int output to pull either high or low, depending on the output polarity setting. measuring the voltage on the v dd pin is regarded as monitoring a channel along with the internal, external, and ain channels. the user can select the v dd channel for single-channel measurement by setting bit c4 = 1 and setting bits c0:c2 to all 0s in the control configuration 2 register. when measuring the v dd value, the reference for the adc is sourced from the internal reference. table 8 shows the data format. as the maximum v dd voltage measurable is 7 v, internal scaling is performed on the v dd voltage to match the 2.25 v internal reference value. below is an example of how the transfer function works. v dd = 5 v adc reference = 2.25 v 1 lsb = adc reference/2 10 = 2.25/1024 = 2.226 mv scale factor = full-scale v cc / adc reference = 7/2.25 = 3.07 conversion result = v dd /( scale factor lsb size ) = 5/(3.07 2.226 mv) = 2 dch table 8. v dd data format (v ref = 2.25 v) digital output v dd value (v) binary hex 2.7 01 1000 1011 18b 3 01 1011 0111 1b7 3.5 10 0000 0000 200 4 10 0100 1001 249 4.5 10 1001 0010 292 5 10 1101 1100 2dc 5.5 11 0010 0101 325 6 11 0110 1110 36e 6.5 11 1011 0111 3b7 7 11 1111 1111 3ff on-chip reference the adt7518 has an on-chip 1.2 v band gap reference, which is gained up by a switched capacitor amplifier to give an output of 2.25 v. the amplifier is powered up for the duration of the device monitoring phase and is powered down once monitoring is disabled. this saves on current consumption. the internal reference is used as the reference for the adc. the adc is used for measuring v dd , internal temperature sensor, external temp- erature sensor, and ain inputs. the internal reference is always used when measuring v dd , and the internal and external temp- erature sensors. the external reference is the default power-up reference for the dacs. round robin measurement on power-up, the adt7518 goes into round robin mode but monitoring is disabled. setting bit c0 of the configuration register 1 to 1 enables conversions. it sequences through all the available channels, taking a measurement from each in the following order: v dd , internal temperature sensor, external temperature sensor/(ain1 and ain2), ain3, and ain4. pin 7 and pin 8 can be configured to be either external temperature sensor pins or standalone analog input pins. once conversion is completed on the ain4 channel, the device loops around for another measurement cycle. this method of taking a measure- ment on all the channels in one cycle is called round robin. setting bit c4 of control configuration 2 (address 19h) disables the round robin mode and in turn sets up the single- channel mode. the single-channel mode is where only one channel, e.g., the internal temperature sensor, is measured in each conversion cycle. the time taken to monitor all channels will normally not be of interest, since the most recently measured value can be read at any time. for applications where the round robin time is impor- tant, typical times at 25c are given in the specifications. single-channel measurement setting c4 of the control configuration 2 register enables the single-channel mode and allows the adt7518 to focus on one channel only. a channel is selected by writing to bits c0:c2 in the control configuration 2 register. for example, to select the v dd channel for monitoring, write to the control configuration
adt7518 rev. a | page 24 of 40 2 r e g i ster an d s e t c4 to 1 (if n o t do ne s o a l r e ad y ) , t h en wr i t e a l l 0s t o b i ts c0:c2 . al l s u bs eq uen t co n v ersio n s wil l be done o n t h e v dd c h a n n e l only . t o c h a n g e t h e c h a n n e l s e lec t io n t o the in t e r - nal t e m p era t ur e cha n n e l, wr i t e to t h e c o n t r o l c o nf igura t io n 2 r e g i s t er an d s e t c0 = 1. w h en m e as ur in g in sin g le-c ha nne l mo d e , c o n v e r s i ons on t h e ch a n ne l s e l e c t e d o c c u r d i re c t ly af te r eac h o t h e r . an y co mm unic a t io n t o th e adt751 8 s t o p s the c o n v e r s i ons , but t h e y are re st ar te d o n c e t h e re a d or w r it e o p era t ion is com p let e d . int e rnal t e mp er ature meas urem ent the ad t7518 c o n t a i n s an o n -chi p band ga p t e m p er a t ur e s e n s o r w h os e ou t p ut is dig i t i ze d b y t h e on-chi p ad c. the t e m p era t ur e da t a is s t o r e d in t h e i n ter n al t e m p era t ur e v a l u e r e g i s t er . b e ca us e b o t h p o si t i ve a nd n e g a t i v e t e m p er a t ur es c a n b e m e as ur e d , t h e tem p er a t ur e da t a is s t o r e d in twos co m p lem e n t fo r m a t , as sh o w n in t a b l e 9. the t h er mal cha r ac t e r i s t ics o f t h e m e as ur e m en t s e n s o r co u l d cha n g e a n d , t h er efo r e , a n o f fs et is adde d t o t h e m e as ur e d val u e t o ena b le t h e t r a n s f er f u n c t i o n t o ma t c h t h e t h er mal cha r ac t e r i s t ics. this o f fs et is adde d b e fo r e t h e tem p era t ur e da t a is st o r e d . the o f fs et val u e us e d is s t o r e d i n t h e i n t e r n al t e m p era t ur e o f fs et r e g i s t er . ex t e rnal t e mp er ature meas urem ent the ad t7518 c a n m e as ur e th e t e m p era t ur e o f o n e ext e r n al dio d e s e n s o r o r dio d e - co n n e c te d t r a n sisto r . the fo r w a r d v o l t a g e o f a dio d e o r dio d e-conn e c t e d t r a n sist o r , o p era t e d a t a con s t a n t c u r r en t, exhi b i ts a n e ga t i v e t e m p era t ur e co ef f i cien t o f a b o u t C2 mv/c. u n f o r t una t e l y , be ca us e t h e ab s o lute v a lu e o f v be va r i es f r o m device t o de vice , a nd indivi- d u a l ca lib r a t io n is r e q u ir e d t o n u l l t h is o u t, t h e t e chni q u e is u n su i t abl e for mass p r o d u c t i on. the t e c h niq u e us ed in t h e adt7518 is t o m e as ur e th e c h a n g e in v be w h e n t h e de v i ce is o p er a t e d a t tw o dif f er en t c u r r en ts. thi s is gi v e n b y () n n q kt v be 1 / = ? w h er e: k is b o l t zma n n s co n s tan t . q is the c h a r g e on the ca r r i er . t is t h e a b s o l u te t e m p era t ur e i n k e lvin s . n i s th e ra ti o o f th e t w o curr e n t s . f i gur e 41 s h o w s th e in p u t sig n al co n d i t io nin g u s ed t o m e as ur e t h e output of an e x te r n a l te m p e r a t u r e s e ns or . t h i s f i g u re show s t h e e x te r n a l s e n s or a s a su b s t r at e t r ans i stor , prov i d e d f o r te m p - era t ur e m o ni t o r i n g o n s o me micr o p r o ces s o r s, b u t i t co u l d eq u a ll y w e ll be a d i sc r e t e tra n s i s t o r . i f a d i s c re te t r a n s i stor i s u s e d , t h e c o l l e c tor i s n o t g rou nd e d a n d s h o u ld b e lin k e d t o the bas e . i f a p n p tra n sis t or is us ed , th e b a s e is co nne c t e d t o t h e d C i n p u t and t h e emi t t e r t o t h e d+ i n p u t. i f a n np n tran sis t o r is us ed , th e emi t t e r is co nn ec t e d t o t h e dC in p u t an d t h e b a s e t o t h e d+ in p u t. a 2 n 3906 is r e co mmen d e d as t h e ext e r n al t r a n sis t o r . t o p r e v e n t g r o u nd n o i s e i n t e r f er in g wi t h t h e me as ur emen t, t h e more ne g a t i v e t e r m i n a l of t h e s e ns or i s no t re f e re nc e d to g rou nd, but i s bi a s e d a b ove g rou nd by a n i n te r n a l d i o d e a t t h e dC i n p u t. a s t h e s e n s o r is o p er a t in g in a n o isy en vir o n m e n t , c 1 is p r o v ide d as a n o is e f i lt er . s e e t h e l a yo u t c o nsidera t io n s s e c t io n fo r m o re info r m a t io n on c1. to m e a s u r e ? v be , th e se n s o r i s s w i t ch e d be tw e e n o p e r a t i n g cur - re n t s of i an d n i . t h e re su lt i n g w a ve f o r m i s p a ss e d t h rou g h a lo w-p a s s f i l t er to r e m o v e n o is e , th en t o a ch o p p e r - s t ab ilize d a m plif ier t h a t p e r f o r m s t h e f u nc t i o n s o f a m plif ica t ion and r e c t i- f i c a t i o n of t h e w a ve f o r m to pr o d u c e a d c vo lt a g e prop or t i on a l to ? v be . thi s vo lt age i s me asu r e d b y t h e a d c t o g i ve a te m p e r - a t ur e o u t p u t in 10-b i t tw os co m p lem e n t f o r m a t . t o f u r t h e r r e d u ce t h e ef fe c t s o f n o is e , dig i t a l f i l t er in g is p e r f o r m e d b y a v era g i n g t h e r e s u l t s o f 16 m e asur em en t c y cles. lay o ut c o nsi d er ations dig i t a l b o a r ds c a n b e ele c t r ica l ly n o isy en v i r o n m e n t s, and ca r e m u s t b e t a k e n to p r o t e c t t h e a n alog in p u ts f r o m n o is e , p a r t ic u - la rly w h en m e asur in g t h e v e r y smal l v o l t a g es f r o m a r e m o te d i o d e s e ns or . t h e f o l l ow i n g pr e c aut i ons s h ou l d b e t a ke n : 1. p l ace t h e adt7 518 as c l os e as p o s s i b le t o t h e rem o t e s e n s in g dio d e . pr o v ide d t h a t t h e w o rst n o is e s o u r ces such as clo c k ge n e r a to rs, da t a /a ddr ess b u s e s, a nd c r t s a r e a v o i de d , this dista n ce can be 4 in ch es t o 8 in ch es. 2. ro u t e t h e d+ and dC t r acks clos e t o g e t h er , in p a ral l e l , wi t h g rou nd e d g u ard t r a c k s on e a c h s i d e . prov i d e a g rou nd plan e u n der t h e t r acks, if p o ssi b le. 3. u s e wide tracks t o minimize ind u c t an ce and r e d u ce n o is e p i ck u p . a 10 mi l t r ack min i m u m wid t h and sp acin g is r e co mme n d e d . gn d d+ d? gn d 10 m i l 10 m i l 10 m i l 10 m i l 10 m i l 10 m i l 10 m i l 04879-050 f i gure 5 0 . a r r a ngem ent o f s i gnal t r acks 4. t r y t o minimize th e n u m b er o f co p p er/s older j o in ts, w h ic h ca n ca us e t h er m o cou p le ef fe c t s. w h er e co pp er /s older jo i n ts a r e used , m a k e s u r e th a t th ey a r e i n bo t h th e d + a n d dC p a t h an d a t th e s a me t e m p era t ur e . th er m o co u p le ef fe c t s s h o u ld no t b e a ma jo r p r ob lem b e c a us e 1c co r r es- p o n d s t o a b ou t 240 v , a nd t h er m o co u p le v o l t a g es a r e a b o u t 3 v / c o f t e m p er a t ur e dif f er en ce . u n le s s t h er e a r e tw o t h er m o co uples wi t h a b i g tem p er a t ur e dif f er en t i a l betw een t h em, t h er mo co u p le vol t a g es sh o u ld b e m u c h les s tha n 200 mv .
adt7518 rev. a | page 25 of 40 5. p l ace 0.1 f b y p a s s an d 2,200 pf in p u t f i l t er c a p a ci t o rs c l os e t o th e adt7518. 6. i f th e dis t an ce to th e r e m o t e s e n s o r is m o r e than 8 in ch es, th e us e o f twist e d-p a ir cab l e is reco mm en de d . this wil l w o rk u p t o abou t 6 f e et t o 12 f e et. 7. f o r lo n g dis t an c e s (u p t o 100 f e et), us e s h ie lde d twis t e d- p a ir ca b l e , s u c h as b e lden #8451 micr o p h o n e cab l e . c o nn e c t t h e t w i s te d p a ir to d+ a nd dC an d t h e shield to gnd c l os e t o t h e adt7518. l e a v e t h e r e m o te end o f th e sh i e l d u n c o n n e c te d to a v oi d g r ou nd l o op s . b e ca us e t h e m e as ur emen t t e chniq u e us es s w i t ch e d c u r r en t s o ur ces, exces s i v e ca b l e and/o r f i l t er ca p a c i tan c e can a f f e c t th e m e as ur e m en t. w h en usin g lo ng ca b l es, t h e f i l t er ca p a ci t o r ma y b e re d u c e d or r e move d . c a b l e r e sis t an ce ca n als o in tr o d uce er r o r s. s e r i e s r e sis t a n c e o f 1 ? i n t r o d u c e s ab out 0 . 5 c e r ror . t e m p er a t ure v a l u e f o rma t on e l s b o f th e ad c co r r es p o nds t o 0.25c. the ad c can t h e o r e t i cal l y m e as ur e a t e m p era t ur e s p a n o f 255 c. th e i n t e r n al t e m p era t ur e s e ns o r is gua r a n te e d t o a lo w val u e limi t o f C40 c. i t is p o s s i b le t o m e as ur e t h e f u l l t e m p era t ur e s p a n usin g t h e ext e r n al t e m p er a t ur e s e n s o r . the t e m p era t ur e da t a fo r m a t is shown i n t a bl e 9 . the r e s u l t o f t h e in ter n al o r ext e r n al t e m p er a t u r e m e as ur e- m e n t s is st o r e d in t h e t e m p era t ur e val u e r e g i s t ers, a n d is com- pa r e d wi th lim i ts p r ogra m m e d in t o th e in t e rn al o r e x t e rn al h i gh a nd lo w r e g i ster s. table 9. temp erature data format (in t ern a l an d e x tern al tem p erature) temper ature digital out p ut C40c 11 01 10 0 000 C25c 11 10 01 1 100 C10c 11 11 01 1 000 C0.25c 11 11 11 1 111 0c 00 00 00 0 000 +0.25c 00 00 00 0 001 +10c 00 00 10 1 000 +25c 00 01 10 0 100 +50c 00 11 00 1 000 +75c 01 00 10 1 100 +10 0 c 01 10 01 0 000 +10 5 c 01 10 10 0 100 +12 5 c 01 11 11 0 100 t e m p er a t ur e c o n v ersio n f o r m u l a: p o s i ti ve t e m p er a t u r e = ad c c o d e / 4 n e ga ti ve t e m p er a t u r e = (a d c c o de * C 5 12)/4 * w h er e d b 9 is rem o v e d f r o m t h e ad c co de. inte rr upts the m e as ur e d r e s u l t s f r o m t h e i n t e r n al t e m p er a t ur e s e n s o r , ext e r n al t e m p er a t ur e s e n s o r , v dd p i n, and ai n i n p u ts a r e co m p a r ed wi th th e t hi g h /v hi g h (g r e a t er tha n com p a r is o n ) an d t lo w /v lo w (les s tha n o r eq u a l t o co m p a r is o n ) limi ts. an in t e r - r u p t o c c u rs if t h e m e as ur e m en t exce e d s o r e q ua ls t h e limi t r e g i s t ers. th es e limi ts a r e s t o r e d in o n -chi p r e g i s t ers. n o t e t h a t t h e li mi t r e g i s t e r s a r e 8 b i ts lo ng w h i l e t h e con v ersio n r e s u l t s ar e 10 b i ts lo n g . i f t h e lim i ts a r e n o t m a s k e d , a n y o u t - o f - l i m i t co m - pa ri so n s g e n e ra t e f l a g s tha t a r e s t o r e d in th e i n t e rr u p t s t a t u s 1 r e g i ster (a ddr ess 00h) an d i n ter r u p t s t a t us 2 r e g i ster ( a d d r e s s 0 1 h ) . o n e or more out - of - l i m it re su lt s w i l l c a u s e t h e int/ int o u t p u t t o p u l l ei ther hig h o r lo w dep e ndin g o n t h e o u t p u t p o la r i ty s e t t in g. i t is g o o d desig n p r ac t i c e t o mask o u t in t e r r u p ts f o r c h a n n e ls tha t a r e o f n o co n c er n to th e a p p l ic a t ion. f i gur e 49 s h o w s th e in t e r r u p t s t r u c t ur e f o r th e adt7518. i t g i ve s a bl o c k d i ag r a m re pre s e n t a t i o n of how t h e v a r i ou s me a s u r e m e n t ch an nel s af fe c t t h e i n t / int pi n . ad t7518 registers the ad t7518 c o n t a i n s r e g i s t ers tha t a r e us e d to s t o r e th e r e s u l t s o f ext e r n al a nd i n t e r n al tem p er a t ur e m e as ur emen t s , v dd val u e me as ur e m e n ts, a n alog i n p u t m e as ur e m en ts, hig h and lo w t e m p era t ur e limi ts, s u p p ly v o l t age a nd a n alog i n p u t li mi ts, t o s e t o u t p u t d a c v o l t a g e leve ls, t o co nf igur e m u l t i p u r p o s e p i n s , an d g e n e ral l y t o co n t r o l t h e de vi ce . a des c r i p t ion of t h es e r e g i s t ers fol l o w s. t h e re g i ste r m a p i s d i v i d e d i n to re g i ste r s of 8 bit s . e a ch re g i ste r has i t s own i ndivi d u a l a ddr ess, b u t s o me co n s ist o f da t a t h a t is lin k e d t o o t h e r r e g i s t ers. th es e r e g i s t ers h o ld t h e 10-b i t con v er - s i on re su lt s of me a s u r e m e n t s t a ke n on t h e te m p e r atu r e, v dd , a nd ai n channe ls. f o r exa m ple , t h e eig h t ms bs o f t h e v dd m e as ur e m en t a r e s t o r e d in reg i s t er a d dr es s 06 h, w h i l e t h e tw o ls bs a r e s t o r e d in reg i st er a ddr es s 03h. th es e typ e s o f r e g i s t ers a r e lin k e d s u ch t h a t w h e n t h e l s b r e g i s t er is r e ad f i rs t, t h e msb r e g i s t ers as s o c i a t e d w i t h t h a t lsb r e g i s t er a r e lo ck e d t o p r e v en t a n y u p da t e s. t o unlo ck t h es e m s b r e g i s t ers, t h e us er has o n ly t o re a d a n y on e of t h e m , w h i c h w i l l h a ve t h e e f f e c t of u n l o ck i n g a l l p r evi o us l y loc k e d ms b r e gi s t e r s . s o , f o r th e p r eced i n g e x a m p l e , if reg i st er 03h was r e ad f i rs t, ms b reg i s t ers 06h an d 07 h w o u l d be lo ck e d t o p r e v en t an y u p da t e s t o th em. i f reg i s t er 06h w e r e re ad, t h is re g i ste r and r e g i ste r 0 7 h wou l d b e su bs e q u e n t ly unlo c k e d . l o ck as s o ci at e d m s b re g i s t e r s f i rs t re ad co m m and ls b r e g i st er ou tp u t dat a 04879-051 f i g u re 51. phas e 1 of 1 0 -bit r e ad
adt7518 rev. a | page 26 of 40 unl o c k a s s o ci at e d m s b re g i s t e r s s e co nd re ad co m m and msb r e g i st er ou tp u t dat a 04879-052 f i g u re 52. phas e 2 of 1 0 -bit r e ad i f a n ms b r e g i ster is r e ad f i rs t, i t s co r r es p o n d in g ls b r e g i s t er is n o t lock e d , lea v in g th e use r wi th th e o p ti o n o f j u s t r e a d in g ba ck 8 bit s ( m sb ) of a 1 0 - bit c o n v e r s i on re su lt . r e a d i n g an m s b re g i ste r f i r s t d o e s not l o c k ot h e r m s b re g i ste r s , an d l i ke w i s e re a d i n g a n l s b re g i ste r f i r s t d o e s not l o c k ot h e r l s b re g i ste r s . table 10. a d t7518 r e gisters rd/wr addr ess name power on def a ult 00h interrupt status 1 00h 01h interrupt status 2 00h 02h r e served 03h internal temp and v dd lsbs 00h 04h externa l temp an d ai n 1 t o ain 4 lsbs 00h 05h r e served 00h 06h v dd msbs xxh 07h internal temp ms bs 00h 08h externa l temp ms bs/ain 1 msbs 00h 09h ain 2 msbs 00h 0ah ain 3 msbs 00h 0bh ain 4 msbs 00h 0chC 10h r e served 00h 11h dac a msbs 00h 12h r e served 00h 13h dac b msbs 00h 14h r e served 00h 15h dac c msbs 00h 16h r e served 00h 17h dac d msbs 00h 18h contro l c o nfig ur a t ion 1 00h 19h contro l c o nfig ur a t ion 2 00h 1ah contr o l c o nfigura t ion 3 00h 1bh dac c o nfigur a t io n 00h 1ch ldac conf igur a t i o n 00h 1dh interrupt mask 1 00h 1eh interrupt mask 2 00h 1fh internal temp offset 00h 20h externa l temp off s et 00h 21h internal ana l og te mp offset d8h 22h externa l an alo g t e mp offset d8h 23h v dd v hig h limit c7h 24h v dd v lo w limit 62h 25h internal t hig h limit 64h 26h internal t lo w limit c9h 27h externa l t hig h /a i n 1 v hig h lim i ts ffh 28h externa l t lo w /a i n 1 v lo w limi ts 00h 29hC 2 ah r e served 2bh ain 2 v hig h limit ffh 2bh ain 2 v hig h limit ffh 2ch ain 2 v low lim i t 00h 2dh ain 3 v hig h limit ffh 2eh ain 3 v low lim i t 00h rd/wr addr ess name power - on def a ult 2fh ain 4 v hig h limit ffh 30h ain 4 v low lim i t 00h 31hC 4 ch r e served 4dh device id 03h/0bh/ 07h 4eh manufactu r er s id 41h 4fh silicon r e vision 04h 50hC 7 eh r e served 00h 7fh spi lock status 00h 80hCffh r e served 00h inte rr upt s t a t u s 1 registe r ( r e a d- onl y ) a dd r e ss = 0 0 h t h i s 8 - bit re a d - o n l y re g i ste r re f l e c t s t h e st atu s of s o me of t h e i n t e rr u p t s th a t ca n ca u s e th e int / int pi n to go ac t i ve. thi s re g i ste r i s re s e t by a re a d op e r at i o n , prov i d e d t h a t a n y out - of - li m i t ev en t h a s been co rr ect e d . i t i s also r e se t b y a so ft w a r e r e s e t . table 11. i n ter r upt status 1 register d7 d6 d5 d4 d3 d2 d1 d0 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * * de f a ul t se t t in gs a t po w e r - u p table 12. b i t f u n c t i o n d0 1 whe n the i n ternal temperature value exceeds t hi g h lim i t. any internal tempera t ure reading gr eater than the set li mit will cause an out-of-li m it event. d1 1 whe n interna l t e mperature value exceeds t lo w lim i t. any internal tempera t ure reading less than or equal to t h e set limit will cause an out - of-limit event. d2 this status bit is linked to t h e co nf iguration of pins 7 and 8. if configured for the external tempe rature sensor, thi s bit is 1 whe n the external temperature value the exceeds t hig h limit. the default value for this limit re gi ster is C1c, so any external temperature reading greater than the set limit will cause an out-of-limit event. if configured for ain1 and ain2, this bit is 1 whe n ain1 input voltage exceeds v hig h or v lo w lim i ts. d3 1 whe n externa l t e mperature value exceeds t lo w lim i t. the default value for this limit reg ister is 0c, so any ext e rnal temperature reading less than or equal to the set li mit will cause an out-of-li m it event. d4 1 indicates a fault (open or sh ort) for the external temperature sensor. d 5 1 w h en ain2 vol t age is greate r than its c o rrespondi ng v hig h lim i t. 1 whe n ain 2 v o lta g e is less t h a n or equ a l to it s c o rresponding v low limit. d 6 1 w h en ain3 vol t age is greate r than its c o rrespondi ng v hig h lim i t. 1 whe n ain 3 v o lta g e is less t h a n or equ a l to it s c o rresponding v low limit. d 7 1 w h en ain4 vol t age is greate r than its c o rrespondi ng v hig h lim i t. 1 whe n ain 4 v o lta g e is less t h a n or equ a l to it s c o rresponding v low limit. inte rr upt s t a t u s 2 registe r ( r e a d onl ) [ a dd r e ss = 0 1 h] t h i s 8 - bit re a d - o n l y re g i ste r re f l e c t s t h e st atu s of t h e v dd in t e r - r u p t th a t ca n ca u s e th e in t/ int p i n t o g o ac ti v e . this r e g i s t er is re s e t by a re a d o p e r a t i o n , prov i d e d t h at a n y out - of - l i m it e v e n t has b e en co r r ec t e d . i t is als o r e s e t b y a s o f t wa r e r e s e t.
adt7518 rev. a | page 27 of 40 table 13. interrupt status 2 register d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a 0* n/a n/a n/a n/a * default settings at power-up. table 14. bit function d4 1 when v dd value is greater than its corresponding v high limit. 1 when v dd is less than or equal to its corresponding v low limit. internal temperature value/v dd value register lsbs (read onl) [address = 03h] this 8-bit read-only register stores the two lsbs of the 10-bit temperature reading from the internal temperature sensor and the two lsbs of the 10-bit supply voltage reading. table 15. internal temperature/v dd lsbs d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a n/a v1 lsb t1 lsb n/a n/a n/a n/a 0* 0* 0* 0* * default settings at power-up table 16. bit function d0 lsb of internal temperature value d1 b1 of internal temperature value d2 lsb of v dd value d3 b1 of v dd value external temperature value and analog inputs 1 to 4 register lsbs (readonl) [address = 04h] this is an 8-bit read-only register. bits d2:d7 store the two lsbs of the analog inputs ain2 to ain4. bits d0:d1 store the two lsbs of either the external temperature value or ain1 input value. the type of input for d0 and d1 is selected by bits c1:c2 of the control configuration register 1. table 17. external temperature and ain1 to ain4 lsbs d7 d6 d5 d4 d3 d2 d1 d0 a4 a4 lsb a3 a3 lsb a2 a2 lsb t/a t/a lsb 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up table 18. bit function d0 lsb of external temperature value or ain1 value d1 bit 1 of external temperature value or ain1 value d2 lsb of ain2 value d3 bit 1 of ain2 value d4 lsb of ain3 value d5 bit 1 of ain3 value d6 lsb of ain4 value d7 bit 1 of ain4 value v dd value register msbs (read-only) address = 6h this 8-bit read-only register stores the supply voltage value. the eight msbs of the 10-bit value are stored in this register. table 19. v dd value msbs d7 d6 d5 d4 d3 d2 d1 d0 v9 v8 v7 v6 v5 v4 v3 v2 x* x* x* x* x* x* x* x* * loaded with v dd value after power-up. internal temperature value register msbs (readonl) [address = 07h] this 8-bit read-only register stores the internal temperature value from the internal temperature sensor in twos complement format. the eight msbs of the 10-bit value are stored in this register. table 20. internal temperature value msbs d7 d6 d5 d4 d3 d2 d1 d0 t9 t8 t7 t6 t5 t4 t3 t2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up external temperature value or analog input ain1 register msbs (read-only) address = 08h this 8-bit read-only register stores, if selected, the external temperature value or the analog input ain1 value. selection is done in the control configuration 1 register. the external temperature value is stored in twos complement format. the eight msbs of the 10-bit value are stored in this register. table 21. external temperatur e value/analog inputs msbs d7 d6 d5 d4 d3 d2 d1 d0 t/a9 t/a8 t/a7 t/a6 t/a5 t/a4 t/a3 t/a2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up ain2 register msbs (read) [address = 09h] this 8-bit read register contains the eight msbs of the ain2 analog input voltage word. the value in this register is com- bined with bits d2:3 of the external temperature value and analog inputs 1 to 4 register lsbs, address 04h, to give the full 10-bit conversion result of the analog value on the ain2 pin. table 22. ain2 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up ain3 register msbs (read) [address = 0ah] this 8-bit read register contains the eight msbs of the ain3 analog input voltage word. the value in this register is com- bined with bits d4:5 of the external temperature value and analog inputs 1 to 4 register lsbs, address 04h, to give the full 10-bit conversion result of the analog value on the ain3 pin.
adt7518 rev. a | page 28 of 40 table 23. ain3 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up ain4 register msbs (read) [address = 0bh] this 8-bit read register contains the eight msbs of the ain4 analog input voltage word. the value in this register is com- bined with bits d6:7 of the external temperature value and analog inputs 1 to 4 register lsbs, address 04h, to give the full 10-bit conversion result of the analog value on the ain4 pin. table 24. ain4 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up dac a register (read/write) [address = 11h] this 8-bit read/write register contains the eight bits of the dac a word. the value in this register is converted to an analog voltage on the v out -a pin. on power-up, the voltage output on the v out -a pin is 0 v. table 25. dac a d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up dac b register (read/write) [address = 13h] this 8-bit read/write register contains the eight bits of the dac b word. the value in this register is converted to an analog voltage on the v out -b pin. on power-up, the voltage output on the v out -b pin is 0 v. table 26. dac b d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up dac c register (read/write) [address = 15h] this 8-bit read/write register contains the eight bits of the dac c word. the value in this register is converted to an analog voltage on the v out -c pin. on power-up, the voltage output on the v out -c pin is 0 v. table 27. dac c d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up dac d register (read/write) address = 17h this 8-bit read/write register contains the eight bits of the dac d word. the value in this register is converted to an analog voltage on the v out -d pin. on power-up, the voltage output on the v out -d pin is 0 v. table 28. dac d d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up control configuration 1 register (read/write) address = 18h this configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the adt7518. table 29. control configuration 1 d7 d6 d5 d4 d3 d2 d1 d0 pd c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up
adt7518 rev. a | page 29 of 40 table 30. bit function c0 this bit enables/disables conversions in round robin and single-channel mode. adt7518 powers up in round robin mode but monitoring is not initiated until this bit is set. the default = 0. 0 = stop monitoring. 1 = start monitoring. c2:c1 selects between the two differe nt analog inputs on pins 7 and 8. adt7518 powers up with ain1 and ain2 selected. 00 = ain1 and ain2 selected. 01 = undefined. 10 = external tdm selected. 11 = undefined. c3 selects between digital (ldac) and analog inputs (ain3) on pin 9. when ain3 is selected, bit c3 of the control configuration 3 register is masked and has no effect until ldac is selected as the input on pin 9. 0 = ldac selected. 1 = ain3 selected. c4 reserved. write 0 only. c5 0 = enable int/ int output. 1 = disable int/ int output. c6 configures int/ int output polarity. 0 = active low. 1 = active high. pd power-down bit. setting this bit to 1 puts the adt7518 into standby mode. in this mode, both adc and dacs are fully powered down, but the serial interface is still operational. to power up the part again, just write 0 to this bit. control configuration 2 register (read/write) [address = 19h] this configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the adt7518 table 31. control configuration 2 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up table 32. bit function c2:0 in single-channel mode, these bits select between v dd , the internal temperature se nsor, external temperature sensor/ain1, ain2, ain3, and ain4 for conversion. the default is v dd . 000 = v dd . 001 = internal temperature sensor. 010 = external temperature sensor/ain1. (bits c1:c2 of the control configuration 1 register affect this selection). 011 = ain2. 100 = ain3. bit function 101 = ain4. 110C111 = reserved. c3 reserved. c4 selects between single-channel and round robin conver- sion cycle. the default is round robin. 0 = round robin. 1 = single channel. c5 default condition is to average every measurement on all channels 16 times. this bit disables this averaging. channels affected are temperature, analog inputs, and v dd . 0 = enable averaging. 1 = disable averaging. c6 smbus timeout on the serial clock puts a 25 ms limit on the pulse width of the clock, ensuring that a fault on the master scl does not lock up the sda line. 0 = disable smbus timeout. 1 = enable smbus timeout. c7 software reset. setting this bit to 1 causes a software reset. all registers and dac outputs will reset to their default settings. control configuration 3 register (read/write) [address = 1ah] this configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the adt7518 table 33. control configuration 3 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up table 34. bit function c0 selects between fast and slow adc conversion speeds. 0 = adc clock at 1.4 khz. 1 = adc clock at 22.5 khz. d+ and dC analog filters are disabled. c2:1 reserved. write 0 only. c3 0 = ldac pin controls updating of dac outputs. 1 = dac configuration register and ldac configuration register control updating of dac outputs. c4 selects the adc reference to be either internal v ref or v dd for analog inputs. 0 = internal v ref. 1 = v dd . c5 setting this bit selects dac a voltage output to be proportional to the internal temperature measurement. c6 setting this bit selects dac b voltage output to be proportional to the external temperature measurement. c7 reserved. write 0 only.
adt7518 rev. a | page 30 of 40 dac configuration register (read/write) [address = 1bh] this configuration register is an 8-bit read/write register that is used to control the output ranges of all four dacs and also to control the loading of the dac registers if the ldac pin is disabled (bit c3 = 1, control configuration 3 register). table 35. dac configuration d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up table 36. bit function d0 selects the output range of dac a. 0 = 0 v to v ref . 1 = 0 v to 2v ref . d1 selects the output range of dac b. 0 = 0 v to v ref . 1 = 0 v to 2v ref . d2 selects the output range of dac c. 0 = 0 v to v ref . 1 = 0 v to 2v ref . d3 selects the output range of dac d. 0 = 0 v to v ref . 1 = 0 v to 2v ref . d5:d4 00 = a write to any dac register generates ldac command that updates that dac only. 01 = a write to dac b or dac d register generates ldac command that updates dacs a, b or dacs c, d, respectively. 10 = a write to dac d register generates ldac command that updates all four dacs. 11 = ldac command generated from ldac register. d6:d7 reserved. write 0s only. ldac configuration register (write-only) [address = 1ch] this configuration register is an 8-bit write register that is used to control the updating of the quad dac outputs if the ldac pin is disabled and bits d4:d5 of the dac configuration reg- ister are both set to 1. also selects either the internal or external v ref for all four dacs. bits d0:d3 in this register are self-clear- ing, i.e., reading back from this register will always give 0s for these bits. table 37. ldac configuration d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up table 38. bit function d0 writing a 1 to this bit will generate the ldac command to update dac a output only. d1 writing a 1 to this bit will generate the ldac command to update dac b output only. d2 writing a 1 to this bit will generate the ldac command to update dac c output only. d3 writing a 1 to this bit will generate the ldac command to update dac d output only. d4 selects either internal v ref or external v ref for dacs a and b. 0 = external v ref 1 = internal v ref . d5 selects either internal v ref or external v ref for dacs c and d. 0 = external v ref 1 = internal v ref d6:d7 reserved. write 0s only. interrupt mask 1 register (read/write) [address = 1dh] this mask register is an 8-bit read/write register that can be used to mask any interrupts that can cause the int/ int pin to go active. table 39. interrupt mask 1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up table 40. bit function d0 0 = enable internal t high interrupt. 1 = disable internal t high interrupt. d1 0 = enable internal t low interrupt. 1 = disable internal t low interrupt. d2 0 = enable external t high interrupt or ain1 interrupt. 1 = disable external t high interrupt or ain1 interrupt. d3 0 = enable external t low interrupt. 1 = disable external t low interrupt. d4 0 = enable external te mperature fault interrupt.. 1 = disable external temp erature fault interrupt. d5 0 = enable ain2 interrupt. 1 = disable ain2 interrupt. d6 0 = enable ain3 interrupt. 1 = disable ain3 interrupt. d7 0 = enable ain4 interrupt. 1 = disable ain4 interrupt.
adt7518 rev. a | page 31 of 40 interrupt mask 2 register (read/write) [address = 1eh] this mask register is an 8-bit read/write register that can be used to mask any interrupts that can cause the int/ int pin to go active. table 41. interrupt mask 2 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up table 42. bit function d0:d3 reserved. write 0s only. d4 0 = enable v dd interrupts. 1 = disable v dd interrupts. d5:d7 reserved. write 0s only. internal temperature offset register (read/write) [address = 1fh] this register contains the offset value for the internal temp- erature channel. a twos complement number can be written to this register which is then added to the measured result before it is stored or compared to limits. in this way, a one-point cali- bration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view, this may be a very simple method to vary the charac- teristics of the measurement channel if the thermal charac- teristics change. because it is an 8-bit register, the temperature resolution is 1c. table 43. internal temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up external temperature offset register (read/write) [address = 20h] this register contains the offset value for the external temp- erature channel. a twos complement number can be written to this register, which is then added to the measured result before it is stored or compared to limits. in this way, a one-point cali- bration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view, this may be a very simple method to vary the charac- teristics of the measurement channel if the thermal charac- teristics change. because it is an 8-bit register, the temperature resolution is 1c. table 44. external temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up internal analog temperature offset register (read/write) [address = 21h] this register contains the offset value for the internal thermal voltage output. a twos complement number can be written to this register, which is then added to the measured result before it is converted by dac a. varying the value in this register has the effect of varying the temperature span. for example, the output voltage can represent a temperature span of C128c to +127c or even 0c to +127c. in essence, this register changes the position of 0 v on the temperature scale. temperatures other than C128c to +127c will produce an upper deadband on the dac a output. because it is an 8-bit register, the temperature resolution is 1c. the default value is C40c. table 45. internal analog temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 1* 1* 0* 0* 0* * default settings at power-up external analog temperature offset register (read/write) [address = 22h] this register contains the offset value for the external thermal voltage output. a twos complement number can be written to this register which is then added to the measured result before it is converted by dac b. varying the value in this register has the effect of varying the temperature span. for example, the output voltage can represent a temperature span of C128c to +127c or even 0c to +127c. in essence, this register changes the position of 0 v on the temperature scale. temperatures other than C128c to +127c will produce an upper deadband on the dac b output. because it is an 8-bit register, the temperature resolution is 1c. the default value is C40c. table 46. external analog temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 1* 1* 0* 0* 0* * default settings at power-up v dd v high limit register (read/write) [address = 23h] this limit register is an 8-bit read/write register that stores the v dd upper limit, which will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured v dd value has to be greater than the value in this register. the default value is 5.46 v. table 47. v dd v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 0* 0* 1* 1* 1* * default settings at power-up
adt7518 rev. a | page 32 of 40 v dd v low limit register (read/write) [address = 24h] this limit register is an 8-bit read/write register that stores the v dd lower limit, which will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured v dd value has to be less than or equal to the value in this register. the default value is 2.7 v. table 48. v dd v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 1* 1* 0* 0* 0* 1* 0* * default settings at power-up internal t high limit register (read/write) [address = 25h] this limit register is an 8-bit read/write register that stores the twos complement of the internal temperature upper limit, which will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured internal temp- erature value has to be greater than the value in this register. because it is an 8-bit register, the temperature resolution is 1c. the default value is +100c. table 49. internal t high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 1* 1* 0* 0* 1* 0* 0* * default settings at power-up internal t low limit register (read/write) [address = 26h] this limit register is an 8-bit read/write register that stores the twos complement of the internal temperature lower limit, which will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured internal temperature value has to be more negative than or equal to the value in this register. because it is an 8-bit register, the temperature reso- lution is 1c. the default value is C55c. table 50. internal t low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 0* 1* 0* 0* 1* * default settings at power-up external t high /ain1 v high limit register (read/write) [address = 27h] if pins 7 and 8 are configured for the external temperature sensor, this limit register is an 8-bit read/write register that stores the twos complement of the external temperature upper limit, which will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured external temperature value has to be greater than the value in this reg- ister. because it is an 8-bit register, the temperature resolution is 1c. the default value is C1c. if pins 7 and 8 are configured for ain1 and ain2 inputs, this limit register is an 8-bit read/write register that stores the ain1 input upper limit, which will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured ain1 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. because the power-up default settings for pins 7 and 8 are ain1 and ain2 inputs, the default value for this limit register is full-scale voltage. table 51. ain1 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* * default settings at power-up external t low /ain1 v low limit register (read/write) [address = 28h] if pins 7 and 8 are configured for the external temperature sensor, this limit register is an 8-bit read/write register that stores the twos complement of the external temperature lower limit, which will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured external temperature value has to be more negative than or equal to the value in this register. because it is an 8-bit register, the temp- erature resolution is 1c. the default value is 0c. if pins 7 and 8 are configured for ain1 and ain2 inputs, this limit register is an 8-bit read/write register that stores the ain1 input lower limit, which will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured ain1 value has to be less than or equal to the value in this reg- ister. as it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. because the power-up default settings for pins 7 and 8 are ain1 and ain2 inputs, the default value for this limit register is 0 v. table 52. ain1 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up ain2 v high limit register (read/write) [address = 2bh] this limit register is an 8-bit read/write register that stores the ain2 input upper limit, which will cause an interrupt and acti- vate the int/ int output (if enabled). for this to happen, the measured ain2 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is full-scale voltage. table 53. ain2 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* * default settings at power-up
adt7518 rev. a | page 33 of 40 ain2 v low limit register (read/write) [address = 2ch] this limit register is an 8-bit read/write register that stores the ain2 input lower limit, which will cause an interrupt and acti- vate the int/ int output (if enabled). for this to happen, the measured ain2 value has to be less than or equal to the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is 0 v. table 54. ain2 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up ain3 v high limit register (read/write) [address = 2dh] this limit register is an 8-bit read/write register that stores the ain3 input upper limit, which will cause an interrupt and acti- vate the int/ int output (if enabled). for this to happen, the measured ain3 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is full-scale voltage. table 55. ain3 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* * default settings at power-up ain3 v low limit register (read/write) [address = 2eh] this limit register is an 8-bit read/write register that stores the ain3 input lower limit, which will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured ain3 value has to be less than or equal to the value in this register. because it is an 8-bit register, the reso- lution is four times less than the resolution of the 10-bit adc. the default value is 0 v. table 56. ain3 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up ain4 v high limit register (read/write) [address = 2fh] this limit register is an 8-bit read/write register that stores the ain4 input upper limit, which will cause an interrupt and acti- vate the int/ int output (if enabled). for this to happen, the measured ain4 value has to be greater than the value in this register. because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit adc. the default value is full-scale voltage. table 57. ain4 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* * default settings at power-up ain4 v low limit register (read/write) [address = 30h] this limit register is an 8-bit read/write register that stores the ain4 input lower limit, which will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured ain4 value has to be less than or equal to the value in this register. because it is an 8-bit register, the reso- lution is four times less than the resolution of the 10-bit adc. the default value is 0 v. table 58. ain4 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up device id register (read-only) [address = 4dh] this 8-bit read-only register cont ains a device identifier byte: adt7518 = 0bh. manufacturers id register (read-only) [address = 4eh] this register contains the manufacturers identification number. adis id number is 41h. silicon revision register (read-only) [address = 4fh] this register is divided into four lsbs representing the stepping and the four msbs representing the version. the stepping con- tains the manufacturers code for minor revisions or steppings to the silicon. the version is the adt7518 version number. spi lock status register (read-only) [address = 7fh] bit d0 (lsb) of this read-only register indicates whether or not the spi interface is locked. writing to this register will cause the device to malfunction. the default value is 00h. 0 = i 2 c interface. 1 = spi interface selected and locked. serial interface there are two serial interfaces that can be used on this part: i 2 c and spi. the device will power up with the serial interface in i 2 c mode, but it is not locked into this mode. to stay in i 2 c mode, it is recommended that the user tie the cs line to either v cc or gnd. it is not possible to lock the i 2 c mode, but it is possible to select and lock the spi mode.
adt7518 rev. a | page 34 of 40 a b cs ( s t a rt hi g h ) s p i l o cke d o n t h i rd ri s i ng e d g e c s p i f r a m in g ed g e 04879-055 a b cs ( s t art l o w ) spi l o c k e d o n t h i rd ri s i ng e d g e c s p i f ram i n g ed g e f i g u re 53. s e ri al int e r f ace s e lec t ing and l o ck ing s p i proto c o l t o s e le c t an d lo ck t h e in t e r f ace in t o t h e sp i m o de , a n u m b er o f p u ls es m u s t be s e n t down t h e cs lin e (p in 4). th e f o l l o w in g s e c t io n de s c r i b e s h o w t h is is don e . on ce t h e s p i comm unica t io n p r o t o c ol has b een lo c k ed in, i t ca nn o t be u n lo c k e d w h ile t h e device is s t il l p o w e r e d u p . b i t d0 o f th e s p i lo ck sta t us r e g i s t er (a ddr es s 7fh) is s e t t o 1 w h en a s u cces s f u l s p i in t e r f ace lo c k has been accom p lis h e d . t o r e s e t t h e s e r i al i n t e r f ace , t h e us er m u s t p o w e r do wn t h e p a r t an d p o we r it up ag ai n . a s o f t w a re re s e t d o e s not re s e t t h e s e r i a l in t e r f ace . se r i a l i n t e r f ac e se l e c t i o n the cs lin e con t r o ls th e s e lec t ion betw een i 2 c and s p i. f i gur e 53 s h o w s t h e s e le c t io n p r o c es s n e ces s a r y t o lo ck t h e s p i in t e r f ace m o de . t o co mm unica t e t o th e adt75 18 usin g th e s p i p r o t o c ol , s e nd t h r e e p u ls es do w n t h e cs lin e as sh o w n in f i gur e 53. on th e t h ir d r i sin g e d ge (ma r k e d a s c in f i gur e 53), t h e p a r t s e le c t s and lo cks t h e s p i i n ter f ace . the us er is n o w limi t e d to co mm uni - ca tin g t o t h e de vice usin g t h e s p i p r o t o c ol . a s p e r mo st s p i st andards , t h e c s l i ne m u st b e l o w d u r i ng ev er y s p i co mm unic a t ion t o t h e adt7518 and hig h al l o t h e r tim e s. t y p i cal exa m p l es o f h o w t o co nnec t t h e d u al in ter f ace as i 2 c or spi i s s h ow n i n fi g u re 5 4 an d f i g u re 5 5 . t h e f o l l ow i n g secti o n s d e sc ri be i n d e ta il h o w t o u s e th e i 2 c and s p i p r o t o c ols as s o c i a t e d wi th th e adt7518. a d t 7518 cs sd a sc l add v dd v dd i 2 c addre s s = 10 01 000 10 k ? 10 k ? 04879-053 f i g u re 54. t y pic a l i 2 c inter f ac e c o nnec t ion a d t 7518 sc l k do ut cs v dd l o ck and s e l e c t spi s p i f r a m in g ed g e 820 ? 820 ? 82 0 ? di n 04879-054 f i gure 55. t y pic a l s p i inter f ac e conn ec tion i 2 c s e rial in t e r f a c e lik e all i 2 c-com p a t i b le de vices, th e adt7518 has a 7-b i t s e r i a l addr es s. th e f o ur ms bs o f this addr es s f o r th e adt7518 a r e s e t t o 1001. th e three ls bs a r e s e t b y p i n 11, ad d . the add p i n ca n be conf igur ed thr e e wa ys t o g i v e thr e e dif f er en t addr es s o p t i o n s: lo w , f l o a t i ng, an d hig h . s e t t in g t h e add p i n lo w g i ves a s e r i al b u s addr es s o f 1001 000, l e a v in g i t f l o a ting g i v e s th e addr es s 1001 01 0, a n d s e t t in g i t hig h g i v e s t h e addr es s 1001 011 . t h e re c o m m e n d e d pu l l - u p re s i stor v a lu e i s 1 0 k ? . ther e is a n e n ab le/dis ab le b i t fo r t h e s m bus t i m e o u t. w h e n t h is i s e n a b led , t h e s m b u s w i ll tim e o u t a f t e r 25 m s o f n o a c ti vi t y . t o ena b le i t , s e t bi t 6 o f t h e c o n t r o l c o nf igura t io n 2 r e g i s t er . the po w e r - o n d e fa u l t i s wi th t h e s m b u s ti m e o u t d i sa b l e d . the ad t7518 su p p o r ts s m b u s p a c k et er r o r c h e c kin g (p ec), b u t i t s us e is o p t i o n a l . i t is t r ig ger e d b y su p p lyi n g t h e ext r a clo c ks fo r t h e pec b y t e . th e p e c is calc u l a t e d usin g cr c-8. the f r a m e c l o c k s e q u en ce (fcs) co nf o r m s t o cr c-8 b y t h e po l y n o m i n a l () 1 1 2 8 + + + = c o n s u l t t h e s m bus sp e c if ic a t ion ( ww w . s m b u s . o r g ) f o r more info r m a t io n.
adt7518 rev. a | page 35 of 40 the serial bus protocol operates as follows: 1. the master initiates a data transfer by establishing a start condition, defined as a high to low transition on the serial data line sda while the serial clock line scl remains high. this indicates that an address/data stream will follow. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit, which deter- mines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. the peripheral whose address corresponds to the trans- mitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is 0 the master will write to the slave device. if the r/ w bit is 1, the master will read from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the receiver of data. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, since a low to high transition when the clock is high may be interpreted as a stop signal. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device will pull the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. the i 2 c address set up by the add pin is not latched by the device until after this address has been sent twice. on the eighth scl cycle of the second valid communication, the serial bus address is latched in. this is the scl cycle directly after the device has seen its own i 2 c serial bus address. any subsequent changes on this pin will have no effect on the i 2 c serial bus address. writing to the adt7518 depending on the register being written to, there are two different writes for the adt7518. it is not possible to do a block write to this part, i.e., no i 2 c autoincrement. writing to the address pointer register for a subsequent read to read data from a particular register, the address pointer register must contain the address of that register. if it does not, the correct address must be written to the address pointer register by performing a single-byte write operation, as shown in figure 56. the write operation consists of the serial bus address followed by the address pointer byte. no data is written to any of the data registers. a read operation is then performed to read the register. writing data to a register all registers are 8-bit registers, so only one byte of data can be written to each register. writing a single byte of data to one of these read/write registers consists of the serial bus address, the data register address written to the address pointer register, followed by the data byte written to the selected data register. this is illustrated in figure 57. to write to a different register, another start or repeated start is required. if more than one byte of data is sent in one communication operation, the addressed register will repeatedly load until the last data byte is sent. reading data from the adt7518 reading data from the adt7518 is done in a 1-byte operation. reading back the contents of a register is shown in figure 58. the register address had previously been set up by a single-byte write operation to the address pointer register. to read from another register, write to the address pointer register again to set up the relevant register address. thus, block reads are not possible, i.e., no i 2 c autoincrement. spi serial interface the spi serial interface of the adt7518 consists of four wires: cs , sclk, din, and dout. the cs line is used to select the device when more than one devi ce is connected to the serial clock and data lines. the cs line is also used to distinguish between any two separate serial communications (see figure 63 for a graphical explanation). the sclk line is used to clock data in and out of the part. the d in line is used to write to the regis- ters, and the dout line is used to read data back from the registers. the recommended pull-up resistor value is between 500 ? and 820 ?. the part operates in slave mode and requires an externally applied serial clock to the sclk input. the serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. there are two types of serial operations, read and write. com- mand words are used to distinguish read operations from write operations. these command words are given in table 59. address autoincrement is possible in spi mode. table 59. spi command words write read 90h (1001 0000) 91h (1001 0001)
adt7518 rev. a | page 36 of 40 0 1 r/w scl s d a frame 1 serial bus address byte frame 2 address pointer register byte ack. by adt7518 ack. by adt7518 stop by master start by master 0 0 1 a 2 a 1 a p 7 p6 p5 p4 p3 p2 p1 p0 9 1 9 1 04879-056 f i g u re 56. i 2 c w r iti n g t o the a ddr ess p o i n t e r regi st er to sele c t a r e gister f o r a subseque nt r e a d o p er atio n frame 1 serial bus address byte frame 2 address pointer register byte ack. by adt7518 ack. by adt7518 stop by master frame 3 data byte sda (continued) scl (continued) scl sd a start by master 1 0 0 1 a 2 a 1 a 0 p 7 p6 p5 p4 p3 p2 p1 p0 9 d7 d6 d 5 d4 d 3 d 2 d 1 d 0 r/w 1 9 1 9 1 04879-057 ack. by adt7518 f i g u re 57. i 2 c w r iti n g t o the a ddr ess p o i n t e r regi st er f o ll o w ed b y a si ngle b y t e o f d a ta to the s e l ect ed reg i st er 1 sda start by master stop by master no ack. by master ack. by adt7518 scl 9 0 0 1 a 2 a 1 a 0 r/w d7 d6 d5 d4 d3 d2 d1 d0 frame 1 serial bus address byte frame 2 single data byte from adt7518 1 9 1 04879-058 f i g u re 58. i 2 creadi n g a singl e byt e o f d a ta f r om a sel ect e d re g i st e r w r it e o p er atio n f i g u re 5 9 show s t h e t i m i ng d i ag r a m f o r a w r it e op e r a t i o n to t h e adt7518. da t a is c l o c k e d in t o th e r e g i st ers o n th e r i sin g edge o f sclk. w h en t h e cs lin e is hig h , th e d i n an d d o ut lin e s a r e in t h r e e - s t a t e m o de . only w h e n t h e cs g o es f r o m a hig h t o a lo w do es th e p a r t accep t an y da ta o n t h e d i n lin e . i n s p i mo de, t h e addr es s p o i n t e r r e g i s t er is c a p a b l e o f a u t o i n cr em e n t i n g t o t h e n e xt r e g i st er in t h e r e g i s t er ma p wi t h o u t ha vin g t o lo ad t h e addr es s p o in ter r e g i s t er e a ch t i m e . i n f i gur e 5 9 , t h e r e g i s t er addr es s p o r t io n g i v e s t h e f i rs t reg i s t er t h a t wi l l b e wr i t t e n t o . sub s e q u e n t da t a b y te s w i l l b e w r it te n i n to s e qu e n t i a l w r it abl e re g i ste r s . th u s , af te r e a ch d a t a b y te has b e e n w r i t te n i n to a r e g i s t er , t h e addr es s p o in t e r r e g i s t er a u t o i n cr e m en ts i t s val u e t o t h e n e xt a v a i la ble r e g i s t er . the addr es s p o i n t e r reg i s t er wi l l a u t o in cr em en t f r o m 00h t o 3fh a nd wil l lo o p bac k t o s t a r t a g ain a t 00h w h en i t reac h e s 3f h. re a d o p e r a t i o n f i gur e 60 t o f i gur e 62 s h o w t h e timin g dia g ra ms n e ces s a r y t o acco m p lish co r r ec t r e ad o p er a t io n s . t o r e ad b a ck f r o m a r e g- is t e r , f i rs t wr i t e to t h e addr es s p o in t e r r e g i st er wi t h t h e addr ess of t h e re g i ste r t o b e re a d f rom . t h i s op e r a t i o n i s sho w n i n f i g u re 6 0 . f i g u re 6 1 show s t h e pro c e d u r e f o r re a d i n g b a ck a sin g le b y t e o f da ta . th e r e ad comman d is f i rs t s e n t t o t h e p a r t d u r i n g t h e f i rs t eig h t clo c k c y cles. d u r i n g t h e fol l o w in g eig h t clo c k c y cles, t h e da t a con t ai n e d in t h e r e g i s t er s e le c t e d b y t h e a d d r e s s p o i n t e r re g i ste r i s output on to t h e d ou t lin e . d a t a is output on to t h e d ou t lin e on t h e fal l in g edg e o f sclk. f i gur e 6 2 show s t h e pro c e d u r e w h e n re a d i n g d a t a f rom t w o s e qu e n t i a l r e g i s t ers. m u l t i p le da t a r e ads a r e p o s s i b le i n t h e s p i in t e r f ace m o de as t h e addr es s p o i n t e r r e g i s t er is a u t o i n c r em e n t a l. th e addr es s p o in ter r e g i s t er wil l a u to in cr em en t f r o m 00h t o 3fh and wil l lo o p back to s t a r t a g a i n a t 00h w h en i t r e ac h e s 3fh.
adt7518 rev. a | page 37 of 40 d7 d6 d5 d4 d3 d2 d1 d6 d5 d4 d3 d2 d1 d0 d0 d7 1 8 1 8 cs sclk din stop d7 d6 d5 d4 d3 d2 d1 d0 1 8 cs (continued) sclk (continued) data byte register address write command din (continued) 04879-059 start f i gure 59. spi wri t ing to the address p o i n t e r re gi st er f o ll o w e d b y a si ngle b y t e o f d a ta to the s e l ect ed reg i st er d7 din d6 d5 d4 d3 d2 d1 d6 d5 d4 d3 d2 d1 d0 d0 d7 s clk 1 8 1 8 cs stop 04879-060 write command start register address f i gure 60. spi wri t ing to the address p o i n t e r re gi st er to se le ct a re gi ste r f o r a subse q uent re ad o p e r a t i o n d7 d6 d5 d4 d3 d2 d1 x x xx x x x d0 x cs sclk din dout 18 1 8 x xx x x x x d6 d5 d4 d3 d2 d1 d0 xd 7 stop 04879-061 data byte 1 read command start f i g u re 61. spi r e ading a s i ng le b y t e of d a t a f r o m a s e l e c t ed r e g i s t e r
adt7518 rev. a | page 38 of 40 d7 d6 d5 d4 d3 d2 d1 x x x x x x x d0 x cs sclk din dout 1 8 1 8 x xx x x x x d6 d 5 d4 d3 d2 d1 d0 xd 7 cs (continued) sclk (continued) din (continued) dout (continued) stop x x x x x x x x 1 8 d7 d6 d5 d 4 d 3 d2 d1 d0 04879-062 start read command data byte 1 data byte 2 f i g u re 62. spi r e ading t w o b y t e s of d a t a f r o m t w o s e quent i al r e g i s t e r s cs spi read operation write operation 04879-063 f i gure 63. spi cor r ec t use of cs d u ring spi communic at ion smbu s/spi int/ int the ad t7518 i n t/ int o u t p u t is an in t e r r u p t line f o r devices th a t w a n t t o tra d e th ei r a b ili t y t o m a s t e r f o r a n e x tra p i n . i t i s a s l a v e de vi ce and us es t h e s m bu s/s p i i n t/ int t o sig n al th e h o s t de vice tha t i t wan t s t o tal k t o . th e s m b u s/s p i i n t/ int on t h e adt7518 is us ed as an o v er/under limi t in dica to r . the in t/ int p i n h a s a n op en -dr a i n co nf igur a t ion t h a t a l lo ws t h e output s of s e ve r a l d e v i c e s t o b e w i re d - a n d e d to ge t h e r w h en t h e i n t/ int p i n is ac t i v e lo w . u s e c6 o f t h e c o n t r o l c o nf ig-ura tion 1 r e g i s t er t o s e t th e ac t i v e p o l a r i ty o f th e int/ int o u t-p u t. th e p o w e r - u p de fa u l t is ac t i ve lo w . th e int/ int o u t p u t can b e dis a b l ed o r ena b led b y s e t t in g c5 o f th e c o n t ro l c o n f i g - u r a t i on 1 re g i st e r to 1 or 0 , re sp e c t i vely . the in t/ int o u t p u t becom e s ac ti ve w h en ei t h er t h e in ter n al t e m p era t ur e value , t h e ext e r n al t e m p era t ur e value , v dd val u e , o r a n y o f t h e ai n i n p u t va l u es exce e d t h e va l u es i n t h eir co r r es- p o ndin g t hi gh /v hi g h or t lo w /v lo w r e g i s t ers. the int/ int out - p u t g o es inac t i ve a g a i n w h en a co n v ersio n r e s u l t has t h e m e as ur e d va l u e b a ck wi t h in t h e t r i p limi ts a nd w h en t h e s t a t us re g i ste r a s s o c i a t e d w i t h t h e out - of - l i m it e v e n t i s re a d . t h e t w o i n t e rr u p t s t a t us r e gi s t e r s s h o w wh i c h ev en t ca used t h e in t/ int pi n to g o a c t i v e . the in t/ int output re qu i r e s an e x t e r n a l pu l l - u p re s i stor . t h i s ca n be conn ec t e d t o a v o l t a g e dif f er en t f r o m v dd , prov i d e d t h e max i m u m vol t age r a t i n g o f t h e int / int o u t p u t p i n is n o t exce e d e d . th e v a l u e o f t h e p u l l - u p r e sis t o r dep e n d s on t h e a p plic a t ion b u t s h o u ld b e la rg e en o u g h t o a v o i d exces s i v e sink c u r r en ts a t t h e i n t/ int o u t p u t , whic h can h e a t the c h i p an d a f fe c t t h e t e m p e r a t ur e r e adin g . smbus alert respons e the in t/ int p i n b e ha ves t h e s a m e wa y as an s m bus a l er t p i n w h en t h e s m bus/i 2 c in t e rfa c e is se lect e d . i t i s a n o p en - d ra i n output a n d re qu i r e s a pu l l - u p to v dd . s e v e r a l i n t / int output s ca n be wir e -and e d t o g e t h er , s o tha t the co mm on lin e wil l go l o w i f one or m ore of t h e i n t / int o u t p uts g o es lo w . th e p o la r - it y of t h e i n t / int p i n m u st b e s e t ac t i ve lo w fo r a n u m b er o f output s to b e w i re - a n d e d to ge t h e r .
adt7518 rev. a | page 39 of 40 the in t/ int o u t p u t can o p era t e as a n sm b a l e r t fu n c ti o n . s l a v e de vices on t h e s m b u s c a nn o t n o r m al l y sig n al t o t h e m a s t e r tha t t h ey w a n t t o talk , b u t th e sm b a l e r t fu n c ti o n al lo ws th em t o do s o . sm b a l e r t is us ed in co n j u n c t ion wi t h t h e s m bus g e n e ral cal l addr es s. o n e or more i n t / int o u t p u t s can be co nnec t e d t o a co m- mo n sm b a l e r t lin e co nnec t e d t o th e mas t er . w h en t h e sm b a l e r t lin e is p u l l ed lo w b y o n e o f t h e de vices, t h e f o ll o w i n g p r oc ed u r e oc cu r s , a s s h o w n in f i g u r e 6 4 . 1. sm b a l e r t pu l l e d l o w . 2. m a st er ini t i a t e s a r e ad o p er a t ion an d s e n d s t h e aler t r e s- p o n s e addr es s ( a ra = 0001 10 0). this is a g e neral cal l addr ess t h a t m u st n o t b e us e d a s a sp e c if ic de vi ce addr ess. 3. the de v i ces w h os e int/ int output i s l o w re sp ond s to t h e aler t r e s p o n s e addr es s and t h e mas t er r e ads i t s de vice addr ess. a s t h e de vice a ddr ess i s s e ve n b i ts lo ng, a n lsb o f 1 is adde d . t h e addr ess o f t h e d e v i ce is n o w k n o w n and i t ca n be in t e r r oga t ed in t h e us ual wa y . 4. i f m o r e than one de vice s i n t/ int o u t p u t is lo w , the o n e wi t h t h e lo w e s t de vice addr es s wil l ha v e p r io r i ty in acco r - dan c e w i t h n o r m a l s m bus sp e c if ica t ion s . 5. on ce t h e ad t7 518 has r e s p onded t o t h e aler t r e s p o n s e a d d r e s s , it w i l l re s e t it s i n t / int output , prov i d e d t h a t t h e co ndi tion tha t c a us ed t h e o u t-of-limi t ev en t n o lo n g er exis ts a nd tha t t h e sta t us r e g i s t er as s o cia t ed wi t h the o u t- o f - l i m i t ev en t i s r e a d . i f th e sm b a l e r t lin e r e ma in s lo w , th e mas t er wil l s e nd t h e ara aga i n. i t wil l co n t in ue t o do th i s un til all de vi ce s w h ose sm b a l e r t output s we re l o w ha ve r e sp onde d. maste r receives smbalert start alert response address rd ack device address master sends ara and read command device sends its address no ack stop 04879-064 f i g u re 64. int / int re sp o n ds to smb a lert ar a master receives smbalert start alert response address rd ack device address master sends ara and read command device sends its address device ack ack pec no ack stop maste r ack maste r nack device sends its pec data 04879- 065 f i g u re 65. int / int re sp o n ds to smb a lert ar a w i th p a ck et e r ror c h eck ing (pe c )
adt7518 rev. a | page 40 of 40 outline dimensions 16 9 8 1 pin 1 sea t i n g pl a n e 0. 0 1 0 0. 0 0 4 0. 012 0. 008 0. 025 bs c 0. 01 0 0. 00 6 0. 050 0. 016 8 0 coplanarity 0.004 0. 065 0. 049 0. 069 0. 053 0. 154 bs c 0. 236 bs c compliant to jedec standards mo-137ab 0 . 193 bs c f i gure 66. 1 6 -l ead shrink sm al l o u t lin e p a ckage [qs o p ] (r q - 16) d i mensions in in ch es ordering guide model temperature r a nge dac resolution package description package option minimum quantities/ree l adt7518arq C40c to +120c 8 bi ts 16-lead qsop rq-16 n/a adt7518arq-r eel C40c to +120c 8 bits 16-lead qsop rq-16 2,500 adt7518arq-r eel7 C40c to +120c 8 bits 16-lead qsop rq-16 1,000 adt7518arqz 1 C40c to +120c 8 bits 16-lead qsop rq-16 n/a adt7518arqz- reel 1 C40c to +120c 8 bits 16-lead qsop rq-16 2,500 adt7518arqz- reel7 1 C40c to +120c 8 bits 16-lead qsop rq-16 1,000 1 z = pb-free part. purchase o f licensed i 2 c co mponents of analog devices or one of its sublicensed associated companies c o nveys a lic e nse f o r the p u r c ha ser und e r the phi lips i 2 c pa tent rig h ts to us e these c o mponent s in a n i 2 c system, pr ovid ed tha t the s y stem c o nf or ms to the i 2 c sta n da rd specif ica t ion a s de f i ned by philips. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c04879-0-8/04(a)

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